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📄 sram.lst

📁 指纹识别源代码,用于智能门紧,还有配合MF800卡使用
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 560   3                              testgroup++;
 561   3                      }while(testgroup);
 562   2              }
 563   1              return TRUE;
 564   1      }
 565          /////////////////////////////////////////////////////////////////////////
 566          
C51 COMPILER V7.01  SRAM                                                                   03/08/2007 12:09:36 PAGE 11  

ASSEMBLY LISTING OF GENERATED OBJECT CODE


             ; FUNCTION _ram_readp0 (BEGIN)
                                           ; SOURCE LINE # 17
;---- Variable 'posi' assigned to Register 'R7' ----
                                           ; SOURCE LINE # 18
                                           ; SOURCE LINE # 20
0000 C2A5              CLR     SRAMA16
                                           ; SOURCE LINE # 21
0002 C2A6              CLR     SRAMA17
                                           ; SOURCE LINE # 22
0004 C2A7              CLR     SRAMA18
                                           ; SOURCE LINE # 24
0006 8F80              MOV     P0,R7
                                           ; SOURCE LINE # 25
0008 D2A3              SETB    SEL573L
                                           ; SOURCE LINE # 26
000A 00                NOP     
                                           ; SOURCE LINE # 27
000B C2A3              CLR     SEL573L
                                           ; SOURCE LINE # 29
000D E4                CLR     A
000E F580              MOV     P0,A
                                           ; SOURCE LINE # 30
0010 D2A2              SETB    SEL573H
                                           ; SOURCE LINE # 31
0012 00                NOP     
                                           ; SOURCE LINE # 32
0013 C2A2              CLR     SEL573H
                                           ; SOURCE LINE # 34
0015 7580FF            MOV     P0,#0FFH
                                           ; SOURCE LINE # 36
0018 C2A4              CLR     SELK6
                                           ; SOURCE LINE # 37
001A C2B7              CLR     RD
                                           ; SOURCE LINE # 38
001C 00                NOP     
                                           ; SOURCE LINE # 39
;---- Variable 'tempdata' assigned to Register 'R7' ----
001D AF80              MOV     R7,P0
                                           ; SOURCE LINE # 40
001F D2B7              SETB    RD
                                           ; SOURCE LINE # 41
0021 D2A4              SETB    SELK6
                                           ; SOURCE LINE # 42
                                           ; SOURCE LINE # 44
0023         ?C0001:
0023 22                RET     
             ; FUNCTION _ram_readp0 (END)

             ; FUNCTION _ram_writep0 (BEGIN)
                                           ; SOURCE LINE # 46
;---- Variable 'writechar' assigned to Register 'R5' ----
;---- Variable 'posi' assigned to Register 'R7' ----
                                           ; SOURCE LINE # 47
                                           ; SOURCE LINE # 48
0000 C2A5              CLR     SRAMA16
                                           ; SOURCE LINE # 49
0002 C2A6              CLR     SRAMA17
                                           ; SOURCE LINE # 50
0004 C2A7              CLR     SRAMA18
C51 COMPILER V7.01  SRAM                                                                   03/08/2007 12:09:36 PAGE 12  

                                           ; SOURCE LINE # 52
0006 8F80              MOV     P0,R7
                                           ; SOURCE LINE # 53
0008 D2A3              SETB    SEL573L
                                           ; SOURCE LINE # 54
000A 00                NOP     
                                           ; SOURCE LINE # 55
000B C2A3              CLR     SEL573L
                                           ; SOURCE LINE # 57
000D E4                CLR     A
000E F580              MOV     P0,A
                                           ; SOURCE LINE # 58
0010 D2A2              SETB    SEL573H
                                           ; SOURCE LINE # 59
0012 00                NOP     
                                           ; SOURCE LINE # 60
0013 C2A2              CLR     SEL573H
                                           ; SOURCE LINE # 62
0015 8D80              MOV     P0,R5
                                           ; SOURCE LINE # 63
0017 C2A4              CLR     SELK6
                                           ; SOURCE LINE # 64
0019 C2B6              CLR     WR
                                           ; SOURCE LINE # 65
001B 00                NOP     
                                           ; SOURCE LINE # 66
001C D2B6              SETB    WR
                                           ; SOURCE LINE # 67
001E D2A4              SETB    SELK6
                                           ; SOURCE LINE # 68
0020 22                RET     
             ; FUNCTION _ram_writep0 (END)

             ; FUNCTION _ram_read (BEGIN)
                                           ; SOURCE LINE # 70
;---- Variable 'low16posi' assigned to Register 'R6/R7' ----
;---- Variable 'high3posi' assigned to Register 'R5' ----
                                           ; SOURCE LINE # 71
                                           ; SOURCE LINE # 76
0000 C2A5              CLR     SRAMA16
                                           ; SOURCE LINE # 77
0002 C2A6              CLR     SRAMA17
                                           ; SOURCE LINE # 78
0004 C2A7              CLR     SRAMA18
                                           ; SOURCE LINE # 79
0006 ED                MOV     A,R5
                                           ; SOURCE LINE # 81
0007 30E002            JNB     ACC.0,?C0003
000A D2A5              SETB    SRAMA16
000C         ?C0003:
                                           ; SOURCE LINE # 82
000C 30E102            JNB     ACC.1,?C0004
000F D2A6              SETB    SRAMA17
0011         ?C0004:
                                           ; SOURCE LINE # 83
0011 30E202            JNB     ACC.2,?C0005
0014 D2A7              SETB    SRAMA18
0016         ?C0005:
                                           ; SOURCE LINE # 89
0016 8F80              MOV     P0,R7
                                           ; SOURCE LINE # 90
0018 D2A3              SETB    SEL573L
C51 COMPILER V7.01  SRAM                                                                   03/08/2007 12:09:36 PAGE 13  

                                           ; SOURCE LINE # 91
001A 00                NOP     
                                           ; SOURCE LINE # 92
001B C2A3              CLR     SEL573L
                                           ; SOURCE LINE # 94
001D 8E80              MOV     P0,R6
                                           ; SOURCE LINE # 95
001F D2A2              SETB    SEL573H
                                           ; SOURCE LINE # 96
0021 00                NOP     
                                           ; SOURCE LINE # 97
0022 C2A2              CLR     SEL573H
                                           ; SOURCE LINE # 99
0024 7580FF            MOV     P0,#0FFH
                                           ; SOURCE LINE # 101
0027 C2A4              CLR     SELK6
                                           ; SOURCE LINE # 102
0029 C2B7              CLR     RD
                                           ; SOURCE LINE # 103
002B 00                NOP     
                                           ; SOURCE LINE # 104
;---- Variable 'tempdata' assigned to Register 'R7' ----
002C AF80              MOV     R7,P0
                                           ; SOURCE LINE # 105
002E D2B7              SETB    RD
                                           ; SOURCE LINE # 106
0030 D2A4              SETB    SELK6
                                           ; SOURCE LINE # 107
                                           ; SOURCE LINE # 108
0032         ?C0006:
0032 22                RET     
             ; FUNCTION _ram_read (END)

             ; FUNCTION _ram_write (BEGIN)
                                           ; SOURCE LINE # 110
;---- Variable 'low16posi' assigned to Register 'R6/R7' ----
;---- Variable 'writechar' assigned to Register 'R3' ----
;---- Variable 'high3posi' assigned to Register 'R5' ----
                                           ; SOURCE LINE # 111
                                           ; SOURCE LINE # 113
0000 C2A5              CLR     SRAMA16
                                           ; SOURCE LINE # 114
0002 C2A6              CLR     SRAMA17
                                           ; SOURCE LINE # 115
0004 C2A7              CLR     SRAMA18
                                           ; SOURCE LINE # 117
0006 ED                MOV     A,R5
                                           ; SOURCE LINE # 119
0007 30E002            JNB     ACC.0,?C0007
000A D2A5              SETB    SRAMA16
000C         ?C0007:
                                           ; SOURCE LINE # 120
000C 30E102            JNB     ACC.1,?C0008
000F D2A6              SETB    SRAMA17
0011         ?C0008:
                                           ; SOURCE LINE # 121
0011 30E202            JNB     ACC.2,?C0009
0014 D2A7              SETB    SRAMA18
0016         ?C0009:
                                           ; SOURCE LINE # 128
0016 8F80              MOV     P0,R7
                                           ; SOURCE LINE # 129
C51 COMPILER V7.01  SRAM                                                                   03/08/2007 12:09:36 PAGE 14  

0018 D2A3              SETB    SEL573L
                                           ; SOURCE LINE # 130
001A 00                NOP     
                                           ; SOURCE LINE # 131
001B C2A3              CLR     SEL573L
                                           ; SOURCE LINE # 133
001D 8E80              MOV     P0,R6
                                           ; SOURCE LINE # 134
001F D2A2              SETB    SEL573H
                                           ; SOURCE LINE # 135
0021 00                NOP     
                                           ; SOURCE LINE # 136
0022 C2A2              CLR     SEL573H
                                           ; SOURCE LINE # 138
0024 8B80              MOV     P0,R3
                                           ; SOURCE LINE # 139
0026 C2A4              CLR     SELK6
                                           ; SOURCE LINE # 140
0028 C2B6              CLR     WR
                                           ; SOURCE LINE # 141
002A 00                NOP     
                                           ; SOURCE LINE # 142
002B D2B6              SETB    WR
                                           ; SOURCE LINE # 143
002D D2A4              SETB    SELK6
                                           ; SOURCE LINE # 145
002F 22                RET     
             ; FUNCTION _ram_write (END)

             ; FUNCTION _ram_read16 (BEGIN)
                                           ; SOURCE LINE # 147
;---- Variable 'ramitem8' assigned to Register 'R7' ----
;---- Variable 'ramitem16' assigned to Register 'R5' ----
                                           ; SOURCE LINE # 148
                                           ; SOURCE LINE # 152
0000 C2A5              CLR     SRAMA16
                                           ; SOURCE LINE # 153
0002 C2A6              CLR     SRAMA17
                                           ; SOURCE LINE # 154
0004 C2A7              CLR     SRAMA18
                                           ; SOURCE LINE # 156
0006 ED                MOV     A,R5
                                           ; SOURCE LINE # 157
0007 30E402            JNB     ACC.4,?C0011
000A D2A5              SETB    SRAMA16
000C         ?C0011:
                                           ; SOURCE LINE # 158
000C 30E502            JNB     ACC.5,?C0012
000F D2A6              SETB    SRAMA17
0011         ?C0012:
                                           ; SOURCE LINE # 159
0011 30E602            JNB     ACC.6,?C0013
0014 D2A7              SETB    SRAMA18
0016         ?C0013:
                                           ; SOURCE LINE # 166
0016 ED                MOV     A,R5
0017 C4                SWAP    A
0018 54F0              ANL     A,#0F0H
001A FE                MOV     R6,A
001B EF                MOV     A,R7
001C C4                SWAP    A
001D 540F              ANL     A,#0FH
C51 COMPILER V7.01  SRAM                                                                   03/08/2007 12:09:36 PAGE 15  

001F 4E                ORL     A,R6
0020 FD                MOV     R5,A
                                           ; SOURCE LINE # 167
0021 EF                MOV     A,R7
0022 C4                SWAP    A
0023 54F0              ANL     A,#0F0H
0025 FF                MOV     R7,A
                                           ; SOURCE LINE # 169
0026 8D80              MOV     P0,R5
                                           ; SOURCE LINE # 170
0028 D2A2              SETB    SEL573H
                                           ; SOURCE LINE # 171
002A 00                NOP     
                                           ; SOURCE LINE # 172
002B C2A2              CLR     SEL573H
002D         ?C0016:
                                           ; SOURCE LINE # 177
                                           ; SOURCE LINE # 178
002D 8F80              MOV     P0,R7
                                           ; SOURCE LINE # 179
002F D2A3              SETB    SEL573L
                                           ; SOURCE LINE # 180
0031 00                NOP     
                                           ; SOURCE LINE # 181
0032 C2A3              CLR     SEL573L
                                           ; SOURCE LINE # 183
0034 7580FF            MOV     P0,#0FFH
                                           ; SOURCE LINE # 185
0037 C2A4              CLR     SELK6

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