📄 ts.lst
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C51 COMPILER V7.01 TS 03/08/2007 12:09:38 PAGE 1
C51 COMPILER V7.01, COMPILATION OF MODULE TS
OBJECT MODULE PLACED IN ts.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE ts.c OPTIMIZE(7,SPEED) REGFILE(.\fingerPRJ.ORC) BROWSE FLOATFUZZY(0) NOAREG
-S DEBUG OBJECTEXTEND CODE
stmt level source
1 #include "reg58.h"
2 #include "intrins.h"
3
4 #define _TS_C_
5 #include "ts.h"
6
7 #include "sram.h"
8 #include "define.h"
9 #include "system.h"
10 /////////////////////////////////////////////////////////////////////
11 bit gettsdata(unsigned short index)
12 {
13 1 //unsigned char page;
14 1 //unsigned char startadd;
15 1 unsigned short startadd;
16 1
17 1 if(index>=400)return FALSE;
18 1
19 1
20 1 //page=index/64+PAGETSSTART;
21 1
22 1 //startadd=(index%64)*4;
23 1 startadd=index*4+PAGETSSTART*256;
24 1
25 1 tempbuff[0]=ram_read(startadd,0);
26 1 if(tempbuff[0]>=24)
27 1 {
28 2 tempbuff[0]=0;
29 2 ram_write(startadd,0,0);
30 2
31 2 }
32 1 tempbuff[1]=ram_read(startadd+1,0);
33 1 if(tempbuff[1]>=60)
34 1 {
35 2 tempbuff[0]=0;
36 2 ram_write(startadd+1,0,0);
37 2
38 2 }
39 1 tempbuff[2]=ram_read(startadd+2,0);
40 1 if(tempbuff[2]>=24)
41 1 {
42 2 tempbuff[2]=0;
43 2 ram_write(startadd+2,0,0);
44 2
45 2 }
46 1 tempbuff[3]=ram_read(startadd+3,0);
47 1 if(tempbuff[3]>=60)
48 1 {
49 2 tempbuff[3]=0;
50 2 ram_write(startadd+3,0,0);
51 2
52 2 }
53 1
54 1 return TRUE;
C51 COMPILER V7.01 TS 03/08/2007 12:09:38 PAGE 2
55 1
56 1 }
57
58 /////////////////////////////////////////////////////////////////////
59 void writets(unsigned short index)
60 {
61 1 //unsigned char page;
62 1 //unsigned char startadd;
63 1 unsigned short startadd;
64 1 if(index>=400)return ;
65 1
66 1 //page=index/64+PAGETSSTART;
67 1
68 1 //startadd=(index%64)*4;
69 1 startadd=index*4+PAGETSSTART*256;
70 1
71 1 ram_write(startadd,0,tempbuff[0]);
72 1 ram_write(startadd+1,0,tempbuff[1]);
73 1 ram_write(startadd+2,0,tempbuff[2]);
74 1 ram_write(startadd+3,0,tempbuff[3]);
75 1 }
76 /////////////////////////////////////////////////////////////////////
77
78 void clearts()
79 {
80 1 unsigned short i;
81 1 for(i=0;i<16;i++)tempbuff[i]=0;
82 1
83 1 i=PAGETSSTART*16;
84 1
85 1 for(;i<(PAGETSEND+1)*16;i++)
86 1 {
87 2 ram_write16(i,i>>8);
88 2 ram_read16(i,i>>8);
89 2 if(tempbuff[0])
90 2 {
91 3 _nop_();
92 3 }
93 2 }
94 1 }
95 /////////////////////////////////////////////////////////////////////
96
97 /////////////////////////////////////////////////////////////////////
C51 COMPILER V7.01 TS 03/08/2007 12:09:38 PAGE 3
ASSEMBLY LISTING OF GENERATED OBJECT CODE
; FUNCTION _gettsdata (BEGIN)
; SOURCE LINE # 11
;---- Variable 'index' assigned to Register 'R6/R7' ----
; SOURCE LINE # 12
; SOURCE LINE # 17
0000 C3 CLR C
0001 EF MOV A,R7
0002 9490 SUBB A,#090H
0004 EE MOV A,R6
0005 9401 SUBB A,#01H
0007 4001 JC ?C0001
0009 22 RET
000A ?C0001:
; SOURCE LINE # 23
000A EF MOV A,R7
000B 7802 MOV R0,#02H
000D ?C0017:
000D C3 CLR C
000E 33 RLC A
000F CE XCH A,R6
0010 33 RLC A
0011 CE XCH A,R6
0012 D8F9 DJNZ R0,?C0017
0014 2400 ADD A,#00H
0016 FF MOV R7,A
0017 EE MOV A,R6
0018 3401 ADDC A,#01H
;---- Variable 'startadd' assigned to Register 'DPTR' ----
001A 8F82 MOV DPL,R7
001C F583 MOV DPH,A
; SOURCE LINE # 25
001E FE MOV R6,A
001F E4 CLR A
0020 FD MOV R5,A
0021 120000 E LCALL _ram_read
0024 7800 E MOV R0,#LOW tempbuff
0026 EF MOV A,R7
0027 F6 MOV @R0,A
; SOURCE LINE # 26
0028 C3 CLR C
0029 9418 SUBB A,#018H
002B 4008 JC ?C0003
; SOURCE LINE # 27
; SOURCE LINE # 28
002D E4 CLR A
002E F6 MOV @R0,A
; SOURCE LINE # 29
002F AF82 MOV R7,DPL
0031 FB MOV R3,A
0032 120000 E LCALL _ram_write
; SOURCE LINE # 31
0035 ?C0003:
; SOURCE LINE # 32
0035 E582 MOV A,DPL
0037 2401 ADD A,#01H
0039 FF MOV R7,A
003A E4 CLR A
003B 3583 ADDC A,DPH
003D FE MOV R6,A
C51 COMPILER V7.01 TS 03/08/2007 12:09:38 PAGE 4
003E E4 CLR A
003F FD MOV R5,A
0040 120000 E LCALL _ram_read
0043 7800 E MOV R0,#LOW tempbuff+01H
0045 EF MOV A,R7
0046 F6 MOV @R0,A
; SOURCE LINE # 33
0047 C3 CLR C
0048 943C SUBB A,#03CH
004A 4011 JC ?C0004
; SOURCE LINE # 34
; SOURCE LINE # 35
004C E4 CLR A
004D 18 DEC R0
004E F6 MOV @R0,A
; SOURCE LINE # 36
004F E582 MOV A,DPL
0051 2401 ADD A,#01H
0053 FF MOV R7,A
0054 E4 CLR A
0055 3583 ADDC A,DPH
0057 FE MOV R6,A
0058 E4 CLR A
0059 FB MOV R3,A
005A 120000 E LCALL _ram_write
; SOURCE LINE # 38
005D ?C0004:
; SOURCE LINE # 39
005D E582 MOV A,DPL
005F 2402 ADD A,#02H
0061 FF MOV R7,A
0062 E4 CLR A
0063 3583 ADDC A,DPH
0065 FE MOV R6,A
0066 E4 CLR A
0067 FD MOV R5,A
0068 120000 E LCALL _ram_read
006B 7800 E MOV R0,#LOW tempbuff+02H
006D EF MOV A,R7
006E F6 MOV @R0,A
; SOURCE LINE # 40
006F C3 CLR C
0070 9418 SUBB A,#018H
0072 4010 JC ?C0005
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