eth_smsc911x.h

Hermit-at-1.1.3,一款bootloader

#ifndef _HERMIT_ETH_SMSC911X_H_
#define _HERMIT_ETH_SMSC911X_H_

#define LAN_CSBASE 0xB2000000 /*A500*/

typedef unsigned char BOOLEAN;
typedef unsigned char BYTE;
typedef unsigned short WORD;
typedef unsigned long DWORD;

typedef struct _PLATFORM_DATA {
        DWORD           dwBitWidth;
        DWORD           dwIdRev;
        DWORD           dwIrq;
        void            *dev_id;
} PLATFORM_DATA, *PPLATFORM_DATA;

typedef struct _DMA_XFER 
{
        DWORD dwLanReg;
        DWORD *pdwBuf;
        DWORD dwDmaCh;
        DWORD dwDwCnt;
        BOOLEAN fMemWr;
} DMA_XFER;

typedef struct _FLOW_CONTROL_PARAMETERS
{
        DWORD MaxThroughput;
        DWORD MaxPacketCount;
        DWORD PacketCost;
        DWORD BurstPeriod;
        DWORD IntDeas;
} FLOW_CONTROL_PARAMETERS, *PFLOW_CONTROL_PARAMETERS;


typedef struct _PRIVATE_DATA {
	DWORD dwLanBase;
	DWORD dwIdRev;
	DWORD dwFpgaRev;
	struct net_device *dev;

	BOOLEAN LanInitialized;

	DWORD dwTxDmaCh;
	BOOLEAN TxDmaChReserved;
	DMA_XFER TxDmaXfer;
	DWORD dwTxDmaThreshold;
	DWORD dwTxQueueDisableMask;
	struct sk_buff *TxSkb;
	BOOLEAN TxInitialized;

	DWORD dwRxDmaCh;
	struct sk_buff *RxSkb;
	BOOLEAN RxDmaChReserved;
	DWORD dwRxDmaThreshold;
	BOOLEAN RxCongested;
	DWORD dwRxOffCount;
	BOOLEAN RxOverrun;
	DWORD RxOverrunCount;
	DWORD RxStatusDWReadCount;
	DWORD RxDataDWReadCount;
	DWORD RxPacketReadCount;
	DWORD RxFastForwardCount;
	DWORD RxPioReadCount;
	DWORD RxDmaReadCount;
	DWORD RxCongestedCount;
	DWORD RxDumpCount;
	DWORD LastReasonForReleasingCPU;
	DWORD LastRxStatus1;
	DWORD LastRxStatus2;
	DWORD LastRxStatus3;
	DWORD LastIntStatus1;
	DWORD LastIntStatus2;
	DWORD LastIntStatus3;
	DWORD RxUnloadProgress;
	DWORD RxUnloadPacketProgress;
	DWORD RxMaxDataFifoSize;

	DWORD RxFlowCurrentThroughput;
	DWORD RxFlowCurrentPacketCount;
	DWORD RxFlowCurrentWorkLoad;
	BOOLEAN MeasuringRxThroughput;
	DWORD RxFlowMeasuredMaxThroughput;
	DWORD RxFlowMeasuredMaxPacketCount;

#define RX_FLOW_ACTIVATION	(4UL)

#define RX_FLOW_DEACTIVATION (25UL)
	DWORD RxFlowMaxWorkLoad;

	FLOW_CONTROL_PARAMETERS RxFlowParameters;

	DWORD RxFlowBurstWorkLoad;
	DWORD RxFlowBurstMaxWorkLoad;
	BOOLEAN RxFlowControlActive;
	BOOLEAN RxFlowBurstActive;
	DWORD RxInterrupts;

#define GPT_SCHEDULE_DEPTH	(3)
	void *GptFunction[GPT_SCHEDULE_DEPTH];
	DWORD GptCallTime[GPT_SCHEDULE_DEPTH];
	DWORD Gpt_scheduled_slot_index;

	BOOLEAN Running;

	DWORD dwPhyAddress;
	DWORD dwPhyId;
#ifdef USE_LED1_WORK_AROUND
	DWORD NotUsingExtPhy;
#endif
	BYTE bPhyModel;
	BYTE bPhyRev;
	DWORD dwLinkSpeed;
	DWORD dwLinkSettings;
	DWORD dwRemoteFaultCount;
	BOOLEAN StopLinkPolling;
	WORD wLastADV;
	WORD wLastADVatRestart;
#ifdef USE_PHY_WORK_AROUND
#define MIN_PACKET_SIZE (64)
	DWORD dwTxStartMargen;
	BYTE LoopBackTxPacket[MIN_PACKET_SIZE];
	DWORD dwTxEndMargen;
	DWORD dwRxStartMargen;
	BYTE LoopBackRxPacket[MIN_PACKET_SIZE];
	DWORD dwRxEndMargen;
	DWORD dwResetCount;
#endif

	BOOLEAN SoftwareInterruptSignal;

	PLATFORM_DATA PlatformData;

#define SMSC_IF_NAME_SIZE	(10)
	char ifName[SMSC_IF_NAME_SIZE];

	/* for Rx Multicast work around */
	volatile DWORD HashLo;
	volatile DWORD HashHi;
	volatile BOOLEAN MulticastUpdatePending;
	volatile DWORD set_bits_mask;
	volatile DWORD clear_bits_mask;

} PRIVATE_DATA, *PPRIVATE_DATA;


#define IS_REV_A(privData)	((privData->dwIdRev&0x0000FFFFUL)==0UL)

//Below are the register offsets and bit definitions
//  of the Lan911x memory space
#define RX_DATA_FIFO	    (0x00UL)

#define TX_DATA_FIFO        (0x20UL)
#define		TX_CMD_A_INT_ON_COMP_		(0x80000000UL)
#define		TX_CMD_A_INT_BUF_END_ALGN_	(0x03000000UL)
#define		TX_CMD_A_INT_4_BYTE_ALGN_	(0x00000000UL)
#define		TX_CMD_A_INT_16_BYTE_ALGN_	(0x01000000UL)
#define		TX_CMD_A_INT_32_BYTE_ALGN_	(0x02000000UL)
#define		TX_CMD_A_INT_DATA_OFFSET_	(0x001F0000UL)
#define		TX_CMD_A_INT_FIRST_SEG_		(0x00002000UL)
#define		TX_CMD_A_INT_LAST_SEG_		(0x00001000UL)
#define		TX_CMD_A_BUF_SIZE_			(0x000007FFUL)
#define		TX_CMD_B_PKT_TAG_			(0xFFFF0000UL)
#define		TX_CMD_B_ADD_CRC_DISABLE_	(0x00002000UL)
#define		TX_CMD_B_DISABLE_PADDING_	(0x00001000UL)
#define		TX_CMD_B_PKT_BYTE_LENGTH_	(0x000007FFUL)

#define RX_STATUS_FIFO      (0x40UL)
#define		RX_STS_ES_			(0x00008000UL)
#define		RX_STS_MCAST_		(0x00000400UL)
#define RX_STATUS_FIFO_PEEK (0x44UL)
#define TX_STATUS_FIFO		(0x48UL)
#define TX_STATUS_FIFO_PEEK (0x4CUL)
#define ID_REV              (0x50UL)
#define		ID_REV_CHIP_ID_		(0xFFFF0000UL)	// RO
#define		ID_REV_REV_ID_		(0x0000FFFFUL)	// RO

#define INT_CFG				(0x54UL)
#define		INT_CFG_INT_DEAS_	(0xFF000000UL)	// R/W
#define		INT_CFG_IRQ_INT_	(0x00001000UL)	// RO
#define		INT_CFG_IRQ_EN_		(0x00000100UL)	// R/W
#define		INT_CFG_IRQ_POL_	(0x00000010UL)	// R/W Not Affected by SW Reset
#define		INT_CFG_IRQ_TYPE_	(0x00000001UL)	// R/W Not Affected by SW Reset

#define INT_STS				(0x58UL)
#define		INT_STS_SW_INT_		(0x80000000UL)	// R/WC
#define		INT_STS_TXSTOP_INT_	(0x02000000UL)	// R/WC
#define		INT_STS_RXSTOP_INT_	(0x01000000UL)	// R/WC
#define		INT_STS_RXDFH_INT_	(0x00800000UL)	// R/WC
#define		INT_STS_RXDF_INT_	(0x00400000UL)	// R/WC
#define		INT_STS_TX_IOC_		(0x00200000UL)	// R/WC
#define		INT_STS_RXD_INT_	(0x00100000UL)	// R/WC
#define		INT_STS_GPT_INT_	(0x00080000UL)	// R/WC
#define		INT_STS_PHY_INT_	(0x00040000UL)	// RO
#define		INT_STS_PME_INT_	(0x00020000UL)	// R/WC
#define		INT_STS_TXSO_		(0x00010000UL)	// R/WC
#define		INT_STS_RWT_		(0x00008000UL)	// R/WC
#define		INT_STS_RXE_		(0x00004000UL)	// R/WC
#define		INT_STS_TXE_		(0x00002000UL)	// R/WC
#define		INT_STS_ERX_		(0x00001000UL)	// R/WC
#define		INT_STS_TDFU_		(0x00000800UL)	// R/WC
#define		INT_STS_TDFO_		(0x00000400UL)	// R/WC
#define		INT_STS_TDFA_		(0x00000200UL)	// R/WC
#define		INT_STS_TSFF_		(0x00000100UL)	// R/WC
#define		INT_STS_TSFL_		(0x00000080UL)	// R/WC
#define		INT_STS_RDFO_		(0x00000040UL)	// R/WC
#define		INT_STS_RDFL_		(0x00000020UL)	// R/WC
#define		INT_STS_RSFF_		(0x00000010UL)	// R/WC
#define		INT_STS_RSFL_		(0x00000008UL)	// R/WC
#define		INT_STS_GPIO2_INT_	(0x00000004UL)	// R/WC
#define		INT_STS_GPIO1_INT_	(0x00000002UL)	// R/WC
#define		INT_STS_GPIO0_INT_	(0x00000001UL)	// R/WC

#define INT_EN				(0x5CUL)
#define		INT_EN_SW_INT_EN_		(0x80000000UL)	// R/W
#define		INT_EN_TXSTOP_INT_EN_	(0x02000000UL)	// R/W
#define		INT_EN_RXSTOP_INT_EN_	(0x01000000UL)	// R/W
#define		INT_EN_RXDFH_INT_EN_	(0x00800000UL)	// R/W
#define		INT_EN_RXDF_INT_EN_		(0x00400000UL)	// R/W
#define		INT_EN_TIOC_INT_EN_		(0x00200000UL)	// R/W
#define		INT_EN_RXD_INT_EN_		(0x00100000UL)	// R/W
#define		INT_EN_GPT_INT_EN_		(0x00080000UL)	// R/W
#define		INT_EN_PHY_INT_EN_		(0x00040000UL)	// R/W
#define		INT_EN_PME_INT_EN_		(0x00020000UL)	// R/W
#define		INT_EN_TXSO_EN_			(0x00010000UL)	// R/W
#define		INT_EN_RWT_EN_			(0x00008000UL)	// R/W
#define		INT_EN_RXE_EN_			(0x00004000UL)	// R/W
#define		INT_EN_TXE_EN_			(0x00002000UL)	// R/W
#define		INT_EN_ERX_EN_			(0x00001000UL)	// R/W
#define		INT_EN_TDFU_EN_			(0x00000800UL)	// R/W
#define		INT_EN_TDFO_EN_			(0x00000400UL)	// R/W
#define		INT_EN_TDFA_EN_			(0x00000200UL)	// R/W
#define		INT_EN_TSFF_EN_			(0x00000100UL)	// R/W
#define		INT_EN_TSFL_EN_			(0x00000080UL)	// R/W
#define		INT_EN_RDFO_EN_			(0x00000040UL)	// R/W
#define		INT_EN_RDFL_EN_			(0x00000020UL)	// R/W
#define		INT_EN_RSFF_EN_			(0x00000010UL)	// R/W
#define		INT_EN_RSFL_EN_			(0x00000008UL)	// R/W
#define		INT_EN_GPIO2_INT_		(0x00000004UL)	// R/W
#define		INT_EN_GPIO1_INT_		(0x00000002UL)	// R/W
#define		INT_EN_GPIO0_INT_		(0x00000001UL)	// R/W

#define BYTE_TEST				(0x64UL)
#define FIFO_INT				(0x68UL)
#define		FIFO_INT_TX_AVAIL_LEVEL_	(0xFF000000UL)	// R/W
#define		FIFO_INT_TX_STS_LEVEL_		(0x00FF0000UL)	// R/W
#define		FIFO_INT_RX_AVAIL_LEVEL_	(0x0000FF00UL)	// R/W
#define		FIFO_INT_RX_STS_LEVEL_		(0x000000FFUL)	// R/W

#define RX_CFG					(0x6CUL)
#define		RX_CFG_RX_END_ALGN_		(0xC0000000UL)	// R/W
#define			RX_CFG_RX_END_ALGN4_		(0x00000000UL)	// R/W
#define			RX_CFG_RX_END_ALGN16_		(0x40000000UL)	// R/W
#define			RX_CFG_RX_END_ALGN32_		(0x80000000UL)	// R/W
#define		RX_CFG_RX_DMA_CNT_		(0x0FFF0000UL)	// R/W
#define		RX_CFG_RX_DUMP_			(0x00008000UL)	// R/W
#define		RX_CFG_RXDOFF_			(0x00001F00UL)	// R/W
#define		RX_CFG_RXBAD_			(0x00000001UL)	// R/W

#define TX_CFG					(0x70UL)
#define		TX_CFG_TX_DMA_LVL_		(0xE0000000UL)	// R/W
#define		TX_CFG_TX_DMA_CNT_		(0x0FFF0000UL)	// R/W Self Clearing
#define		TX_CFG_TXS_DUMP_		(0x00008000UL)	// Self Clearing
#define		TX_CFG_TXD_DUMP_		(0x00004000UL)	// Self Clearing
#define		TX_CFG_TXSAO_			(0x00000004UL)	// R/W
#define		TX_CFG_TX_ON_			(0x00000002UL)	// R/W
#define		TX_CFG_STOP_TX_			(0x00000001UL)	// Self Clearing

#define HW_CFG					(0x74UL)
#define		HW_CFG_TTM_				(0x00200000UL)	// R/W
#define		HW_CFG_SF_				(0x00100000UL)	// R/W
#define		HW_CFG_TX_FIF_SZ_		(0x000F0000UL)	// R/W
#define		HW_CFG_TR_				(0x00003000UL)	// R/W
#define     HW_CFG_PHY_CLK_SEL_		(0x00000060UL)  // R/W
#define         HW_CFG_PHY_CLK_SEL_INT_PHY_	(0x00000000UL) // R/W
#define         HW_CFG_PHY_CLK_SEL_EXT_PHY_	(0x00000020UL) // R/W
#define         HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040UL) // R/W
#define     HW_CFG_SMI_SEL_			(0x00000010UL)  // R/W
#define     HW_CFG_EXT_PHY_DET_		(0x00000008UL)  // RO
#define     HW_CFG_EXT_PHY_EN_		(0x00000004UL)  // R/W
#define		HW_CFG_32_16_BIT_MODE_	(0x00000004UL)	// RO
#define     HW_CFG_SRST_TO_			(0x00000002UL)  // RO
#define		HW_CFG_SRST_			(0x00000001UL)	// Self Clearing