📄 satadrv.h
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short commandSetEnable2;
short commandSetDefault; /* Command set/feature default */
short ultraDmaMode; /* [88] F 15-14 Reserved
V 13 1 = Ultra DMA mode 5 is selected
0 = Ultra DMA mode 5 is not selected
V 12 1 = Ultra DMA mode 4 is selected
0 = Ultra DMA mode 4 is not selected
V 11 1 = Ultra DMA mode 3 is selected
0 = Ultra DMA mode 3 is not selected
V 10 1 = Ultra DMA mode 2 is selected
0 = Ultra DMA mode 2 is not selected
V 9 1 = Ultra DMA mode 1 is selected
0 = Ultra DMA mode 1 is not selected
V 8 1 = Ultra DMA mode 0 is selected
0 = Ultra DMA mode 0 is not selected
F 7-6 Reserved
F 5 1 = Ultra DMA mode 5 and below are supported
F 4 1 = Ultra DMA mode 4 and below are supported
F 3 1 = Ultra DMA mode 3 and below are supported
F 2 1 = Ultra DMA mode 2 and below are supported
F 1 1 = Ultra DMA mode 1 and below are supported
F 0 1 = Ultra DMA mode 0 is supported*/
short reserved89[39]; /* reserved */
short vendor[32]; /* vendor specific */
short reserved160[96]; /* reserved */
} SATA_PARAM;
typedef enum /* ATAPI */
{
NON_DATA, /* non data command */
OUT_DATA,
IN_DATA
} t_data_dir;
typedef struct sataDev
{
BLK_DEV blkDev; /* must be here */
int ctrl; /* ctrl no. 0 - 1 */
int drive; /* drive no. 0 - 3 */
int blkOffset; /* sector offset */
int nBlocks; /* number of sectors */
char * pBuf; /* Current position in an user buffer */
char * pBufEnd; /* End of user buffer */
t_data_dir direction; /* Transfer direction */
int transCount; /* Number of transfer cycles */
int errNum; /* Error description message number */
/* ATAPI Registers contents */
uint8_t intReason; /* Interrupt Reason Register */
uint8_t status; /* Status Register */
uint16_t transSize; /* Byte Count Register */
} SATA_DEV;
typedef struct sataDrive
{
SATA_PARAM param; /* geometry parameter */
short okMulti; /* MULTI: TRUE if supported */
short okIordy; /* IORDY: TRUE if supported */
short okDma; /* DMA: TRUE if supported */
short okLba; /* LBA: TRUE if supported */
short multiSecs; /* supported max sectors for multiple RW */
short pioMode; /* supported max PIO mode */
short singleDmaMode; /* supported max single word DMA mode */
short multiDmaMode; /* supported max multi word DMA mode */
short ultraDmaMode; /* supported max ultra word DMA mode */
short rwMode; /* RW mode: PIO[0,1,2,3,4] or DMA[0,1,2] */
short rwBits; /* RW bits: 16 or 32 */
short rwPio; /* RW PIO unit: single or multi sector */
short rwDma; /* RW DMA unit: single or multi word */
uint8_t state; /* device state */
uint8_t diagCode; /* diagnostic code */
uint8_t type; /* device type */
STATUS (*Reset) /* pointer to reset function */
(
int ctrl,
int dev
);
SATA_DEV *pAtaDev; /* pointer to ATA block device structure */
} SATA_DRIVE;
typedef struct sataCtrl
{
SATA_DRIVE drive[SATA_MAX_DRIVES]; /* drives per controller */
SEMAPHORE syncSem; /* binary sem for syncronization */
SEMAPHORE rdsyncSem; /* binary sem for syncronization */
SEMAPHORE muteSem; /* mutex sem for mutual-exclusion */
WDOG_ID wdgId; /* watch dog */
BOOL wdgOkay; /* watch dog status */
int semTimeout; /* timeout seconds for sync semaphore */
int wdgTimeout; /* timeout seconds for watch dog */
int ctrlType; /* type of controller */
BOOL installed; /* TRUE if a driver is installed */
BOOL changed; /* TRUE if a card is installed */
int intLevel; /* interrupt level */
int intCount; /* interrupt count */
int intStatus; /* interrupt status */
int drives; /* number of drives in the controller */
int configType; /* or'd configuration flags */
UINT32 globalAddr;
UINT32 portAddr;
} SATA_CTRL;
typedef struct sataType
{
int cylinders; /* number of cylinders */
int heads; /* number of heads */
int sectors; /* number of sectors per track */
int bytes; /* number of bytes per sector */
int precomp; /* precompensation cylinder */
} SATA_TYPE;
typedef struct sataRaw
{ /* this is for ATARAWACCESS ioctl */
UINT cylinder; /* cylinder (0 -> (cylindres-1)) */
UINT head; /* head (0 -> (heads-1)) */
UINT sector; /* sector (1 -> sectorsTrack) */
char *pBuf; /* pointer to buffer (bytesSector * nSecs) */
UINT nSecs; /* number of sectors (1 -> sectorsTrack) */
UINT direction; /* read=0, write=1 */
} SATA_RAW;
#define SATA_SEM_TIMEOUT_DEF 30 /* default timeout for ATA sync sem */
#define SATA_WDG_TIMEOUT_DEF 30 /* default timeout for ATA watch dog */
/* diagnostic code */
#define ATA_DIAG_OK 0x01
/* Device types */
#define SATA_TYPE_NONE 0x00 /* device is faulty or not present */
#define SATA_TYPE_ATA 0x01 /* ATA device */
#define SATA_TYPE_ATAPI 0x02 /* ATAPI device */
#define SATA_TYPE_INIT 255 /* device must be identified */
/* Device states */
#define SATA_DEV_OK 0 /* device is OK */
#define SATA_DEV_NONE 1 /* device absent or does not respond */
#define SATA_DEV_DIAG_F 2 /* device diagnostic failed */
#define SATA_DEV_PREAD_F 3 /* read device parameters failed */
#define SATA_DEV_MED_CH 4 /* medium have been changed */
#define SATA_DEV_NO_BLKDEV 5 /* No block device available */
#define SATA_DEV_INIT 255 /* uninitialized device */
/* control register */
#define ATA_CTL_4BIT 0x8 /* use 4 head bits (wd1003) */
#define ATA_CTL_RST 0x4 /* reset controller */
#define ATA_CTL_IDS 0x2 /* disable interrupts */
/* status register */
#define ATA_STAT_ACCESS (ATA_STAT_BUSY | ATA_STAT_DRQ)
/* device accessible */
#define ATA_STAT_BUSY 0x80 /* controller busy */
#define ATA_STAT_READY 0x40 /* selected drive ready */
#define ATA_STAT_WRTFLT 0x20 /* write fault */
#define ATA_STAT_SEEKCMPLT 0x10 /* seek complete */
#define ATA_STAT_DRQ 0x08 /* data request */
#define ATA_STAT_ECCCOR 0x04 /* ECC correction made in data */
#define ATA_STAT_INDEX 0x02 /* index pulse from selected drive */
#define ATA_STAT_ERR 0x01 /* error detect */
/* size/drive/head register: addressing mode CHS or LBA */
#define ATA_SDH_IBM 0xa0 /* chs, 512 bytes sector, ecc */
#define ATA_SDH_LBA 0xe0 /* lba, 512 bytes sector, ecc */
/* commands */
#define ATA_CMD_RECALIB 0x10 /* recalibrate */
#define ATA_CMD_SEEK 0x70 /* seek */
#define ATA_CMD_READ 0x20 /* read sectors with retries */
#define ATA_CMD_WRITE 0x30 /* write sectors with retries */
#define ATA_CMD_FORMAT 0x50 /* format track */
#define ATA_CMD_DIAGNOSE 0x90 /* execute controller diagnostic */
#define ATA_CMD_INITP 0x91 /* initialize drive parameters */
#define ATA_CMD_READP 0xEC /* identify */
#define ATA_CMD_SET_FEATURE 0xEF /* set features */
#define ATA_CMD_SET_MULTI 0xC6 /* set multi */
#define ATA_CMD_READ_MULTI 0xC4 /* read multi */
#define ATA_CMD_WRITE_MULTI 0xC5 /* write multi */
#define ATA_CMD_READ_DMA 0xC8 /* with retries */
#define ATA_CMD_READ_DMA_NO 0xC9 /* without retries */
#define ATA_CMD_WRITE_DMA 0xCA /* with retries */
#define ATA_CMD_WRITE_DMA_NO 0xCB /* without retries */
/* sub command of ATA_CMD_SET_FEATURE */
#define ATA_SUB_ENABLE_8BIT 0x01 /* enable 8bit data transfer */
#define ATA_SUB_ENABLE_WCACHE 0x02 /* enable write cache */
#define ATA_SUB_SET_RWMODE 0x03 /* set transfer mode */
#define ATA_SUB_DISABLE_RETRY 0x33 /* disable retry */
#define ATA_SUB_SET_LENGTH 0x44 /* length of vendor specific bytes */
#define ATA_SUB_SET_CACHE 0x54 /* set cache segments */
#define ATA_SUB_DISABLE_LOOK 0x55 /* disable read look-ahead feature */
#define ATA_SUB_DISABLE_REVE 0x66 /* disable reverting to power on def */
#define ATA_SUB_DISABLE_ECC 0x77 /* disable ECC */
#define ATA_SUB_DISABLE_8BIT 0x81 /* disable 8bit data transfer */
#define ATA_SUB_DISABLE_WCACHE 0x82 /* disable write cache */
#define ATA_SUB_ENABLE_ECC 0x88 /* enable ECC */
#define ATA_SUB_ENABLE_RETRY 0x99 /* enable retries */
#define ATA_SUB_ENABLE_LOOK 0xaa /* enable read look-ahead feature */
#define ATA_SUB_SET_PREFETCH 0xab /* set maximum prefetch */
#define ATA_SUB_SET_4BYTES 0xbb /* 4 bytes of vendor specific bytes */
#define ATA_SUB_ENABLE_REVE 0xcc /* enable reverting to power on def */
/* transfer modes of ATA_SUB_SET_RWMODE */
#define ATA_PIO_DEF_W 0x00 /* PIO default trans. mode */
#define ATA_PIO_DEF_WO 0x01 /* PIO default trans. mode, no IORDY */
#define ATA_PIO_W_0 0x08 /* PIO flow control trans. mode 0 */
#define ATA_PIO_W_1 0x09 /* PIO flow control trans. mode 1 */
#define ATA_PIO_W_2 0x0a /* PIO flow control trans. mode 2 */
#define ATA_PIO_W_3 0x0b /* PIO flow control trans. mode 3 */
#define ATA_PIO_W_4 0x0c /* PIO flow control trans. mode 4 */
#define ATA_DMA_SINGLE_0 0x10 /* singleword DMA mode 0 */
#define ATA_DMA_SINGLE_1 0x11 /* singleword DMA mode 1 */
#define ATA_DMA_SINGLE_2 0x12 /* singleword DMA mode 2 */
#define ATA_DMA_MULTI_0 0x20 /* multiword DMA mode 0 */
#define ATA_DMA_MULTI_1 0x21 /* multiword DMA mode 1 */
#define ATA_DMA_MULTI_2 0x22 /* multiword DMA mode 2 */
#define ATA_DMA_ULTRA_0 0x40 /* ultraword DMA mode 0 */
#define ATA_DMA_ULTRA_1 0x41 /* ultraword DMA mode 1 */
#define ATA_DMA_ULTRA_2 0x42 /* ultraword DMA mode 2 */
#define ATA_MAX_RW_SECTORS 0x100 /* max sectors per transfer */
/* configuration flags: transfer mode, bits, unit, geometry */
#define ATA_PIO_DEF_0 ATA_PIO_DEF_W /* PIO default mode */
#define ATA_PIO_DEF_1 ATA_PIO_DEF_WO /* PIO default mode, no IORDY */
#define ATA_PIO_0 ATA_PIO_W_0 /* PIO mode 0 */
#define ATA_PIO_1 ATA_PIO_W_1 /* PIO mode 1 */
#define ATA_PIO_2 ATA_PIO_W_2 /* PIO mode 2 */
#define ATA_PIO_3 ATA_PIO_W_3 /* PIO mode 3 */
#define ATA_PIO_4 ATA_PIO_W_4 /* PIO mode 4 */
#define ATA_PIO_AUTO 0x000d /* PIO max supported mode */
#define ATA_DMA_0 0x0002 /* DMA mode 0 */
#define ATA_DMA_1 0x0003 /* DMA mode 1 */
#define ATA_DMA_2 0x0004 /* DMA mode 2 */
#define ATA_DMA_AUTO 0x0005 /* DMA max supported mode */
#define ATA_MODE_MASK 0x000F /* transfer mode mask */
#define ATA_BITS_16 0x0040 /* RW bits size, 16 bits */
#define ATA_BITS_32 0x0080 /* RW bits size, 32 bits */
#define ATA_BITS_MASK 0x00c0 /* RW bits size mask */
#define ATA_PIO_SINGLE 0x0010 /* RW PIO single sector */
#define ATA_PIO_MULTI 0x0020 /* RW PIO multi sector */
#define ATA_PIO_MASK 0x0030 /* RW PIO mask */
#define ATA_DMA_SINGLE 0x0400 /* RW DMA single word */
#define ATA_DMA_MULTI 0x0800 /* RW DMA multi word */
#define ATA_DMA_ULTRA 0x1000 /* RW DMA ultra word */
#define ATA_DMA_MASK 0x1c00 /* RW DMA mask */
#define ATA_GEO_FORCE 0x0100 /* set geometry in the table */
#define ATA_GEO_PHYSICAL 0x0200 /* set physical geometry */
#define ATA_GEO_CURRENT 0x0300 /* set current geometry */
#define ATA_GEO_MASK 0x0300 /* geometry mask */
#define ATA_PIO 0
#define ATA_MDMA 1
#define ATA_UDMA 2
extern STATUS sataDrv (int ctrl, int drives, int vector, int level,
int configType, int semTimeout,
int wdgTimeout);
extern BLK_DEV *sataDevCreate (int ctrl, int drive, int nBlks, int offset);
extern STATUS sataRawio (int ctrl, int drive, SATA_RAW *pAtaRaw);
#endif /* __INCpcsataDrvh */⌨️ 快捷键说明
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