📄 satadrv.h
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#ifndef __INCpcsataDrvh
#define __INCpcsataDrvh
#include "dosFsLib.h"
#include "blkIo.h"
#include "wdLib.h"
#include "private/semLibP.h"
#define IDE_LOCAL 0 /* ctrl type: LOCAL(IDE) */
#define ATA_PCMCIA 1 /* ctrl type: PCMCIA */
#define SATA_MAX_CTRLS 1 /* max number of ATA controller */
#define SATA_MAX_DRIVES 1 /* max number of ATA drives 4 */
/* Global controller registers (128 bytes @ BAR0) */
/* 32 bit regs */
#define HOST_SLOT_STAT 0x00
#define HOST_CTRL 0x40
#define HOST_IRQ_STAT 0x44
#define HOST_PHY_CFG 0x48
#define HOST_BIST_CTRL 0x50
#define HOST_BIST_PTRN 0x54
#define HOST_BIST_STAT 0x58
#define HOST_MEM_BIST_STAT 0x5c
#define HOST_FLASH_CMD 0x70
/* 8 bit regs */
#define HOST_FLASH_DATA 0x74
#define HOST_TRANSITION_DETECT 0x75
#define HOST_GPIO_CTRL 0x76
#define HOST_I2C_ADDR 0x78 /*32 bit */
#define HOST_I2C_DATA 0x7c
#define HOST_I2C_XFER_CNT 0x7e
#define HOST_I2C_CTRL 0x7f
/* HOST_SLOT_STAT bits */
#define HOST_SSTAT_ATTN (1 << 31)
/* HOST_CTRL bits */
#define HOST_CTRL_M66EN (1 << 16) /* M66EN PCI bus signal */
#define HOST_CTRL_TRDY (1 << 17) /* latched PCI TRDY */
#define HOST_CTRL_STOP (1 << 18) /* latched PCI STOP */
#define HOST_CTRL_DEVSEL (1 << 19) /* latched PCI DEVSEL */
#define HOST_CTRL_REQ64 (1 << 20) /* latched PCI REQ64 */
#define HOST_CTRL_GLOBAL_RST (1 << 31) /* global reset */
/*
* Port registers
* (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
*/
#define PORT_REGS_SIZE 0x2000
#define PORT_LRAM 0x0000 /* 31 LRAM slots and PMP regs */
#define PORT_LRAM_SLOT_SZ 0x0080 /* 32 bytes PRB + 2 SGE, ACT... */
#define PORT_PMP 0x0f80 /* 8 bytes PMP * 16 (128 bytes) */
#define PORT_PMP_STATUS 0x0000 /* port device status offset */
#define PORT_PMP_QACTIVE 0x0004 /* port device QActive offset */
#define PORT_PMP_SIZE 0x0008 /* 8 bytes per PMP */
/* 32 bit regs */
#define PORT_CTRL_STAT 0x1000 /* write: ctrl-set, read: stat */
#define PORT_CTRL_CLR 0x1004 /* write: ctrl-clear */
#define PORT_IRQ_STAT 0x1008 /* high: status, low: interrupt */
#define PORT_IRQ_ENABLE_SET 0x1010 /* write: enable-set */
#define PORT_IRQ_ENABLE_CLR 0x1014 /* write: enable-clear */
#define PORT_ACTIVATE_UPPER_ADDR 0x101c
#define PORT_EXEC_FIFO 0x1020 /* command execution fifo */
#define PORT_CMD_ERR 0x1024 /* command error number */
#define PORT_FIS_CFG 0x1028
#define PORT_FIFO_THRES 0x102c
/* 16 bit regs */
#define PORT_DECODE_ERR_CNT 0x1040
#define PORT_DECODE_ERR_THRESH 0x1042
#define PORT_CRC_ERR_CNT 0x1044
#define PORT_CRC_ERR_THRESH 0x1046
#define PORT_HSHK_ERR_CNT 0x1048
#define PORT_HSHK_ERR_THRESH 0x104a
/* 32 bit regs */
#define PORT_PHY_CFG 0x1050
#define PORT_SLOT_STAT 0x1800
#define PORT_CMD_ACTIVATE 0x1c00 /* 64 bit cmd activate * 31 (248 bytes) */
#define PORT_CONTEXT 0x1e04
#define PORT_EXEC_DIAG 0x1e00 /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
#define PORT_PSD_DIAG 0x1e40 /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
#define PORT_SCONTROL 0x1f00
#define PORT_SSTATUS 0x1f04
#define PORT_SERROR 0x1f08
#define PORT_SACTIVE 0x1f0c
/* PORT_CTRL_STAT bits */
#define PORT_CS_PORT_RST (1 << 0) /* port reset */
#define PORT_CS_DEV_RST (1 << 1) /* device reset */
#define PORT_CS_INIT (1 << 2) /* port initialize */
#define PORT_CS_IRQ_WOC (1 << 3) /* interrupt write one to clear */
#define PORT_CS_CDB16 (1 << 5) /* 0=12b cdb, 1=16b cdb */
#define PORT_CS_PMP_RESUME (1 << 6) /* PMP resume */
#define PORT_CS_32BIT_ACTV (1 << 10) /* 32-bit activation */
#define PORT_CS_PMP_EN (1 << 13) /* port multiplier enable */
#define PORT_CS_RDY (1 << 31) /* port ready to accept commands */
/* PORT_IRQ_STAT/ENABLE_SET/CLR */
/* bits[11:0] are masked */
#define PORT_IRQ_COMPLETE (1 << 0) /* command(s) completed */
#define PORT_IRQ_ERROR (1 << 1) /* command execution error */
#define PORT_IRQ_PORTRDY_CHG (1 << 2) /* port ready change */
#define PORT_IRQ_PWR_CHG (1 << 3) /* power management change */
#define PORT_IRQ_PHYRDY_CHG (1 << 4) /* PHY ready change */
#define PORT_IRQ_COMWAKE (1 << 5) /* COMWAKE received */
#define PORT_IRQ_UNK_FIS (1 << 6) /* unknown FIS received */
#define PORT_IRQ_DEV_XCHG (1 << 7) /* device exchanged */
#define PORT_IRQ_8B10B (1 << 8) /* 8b/10b decode error threshold */
#define PORT_IRQ_CRC (1 << 9) /* CRC error threshold */
#define PORT_IRQ_HANDSHAKE (1 << 10) /* handshake error threshold */
#define PORT_IRQ_SDB_NOTIFY (1 << 11) /* SDB notify received */
#define DEF_PORT_IRQ PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | \
PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | \
PORT_IRQ_UNK_FIS
/* bits[27:16] are unmasked (raw) */
#define PORT_IRQ_RAW_SHIFT 16
#define PORT_IRQ_MASKED_MASK 0x7ff
#define PORT_IRQ_RAW_MASK (0x7ff << PORT_IRQ_RAW_SHIFT)
/* ENABLE_SET/CLR specific, intr steering - 2 bit field */
#define PORT_IRQ_STEER_SHIFT 30
#define PORT_IRQ_STEER_MASK (3 << PORT_IRQ_STEER_SHIFT)
/* PORT_CMD_ERR constants */
#define PORT_CERR_DEV 1 /* Error bit in D2H Register FIS */
#define PORT_CERR_SDB 2 /* Error bit in SDB FIS */
#define PORT_CERR_DATA 3 /* Error in data FIS not detected by dev */
#define PORT_CERR_SEND 4 /* Initial cmd FIS transmission failure */
#define PORT_CERR_INCONSISTENT 5 /* Protocol mismatch */
#define PORT_CERR_DIRECTION 6 /* Data direction mismatch */
#define PORT_CERR_UNDERRUN 7 /* Ran out of SGEs while writing */
#define PORT_CERR_OVERRUN 8 /* Ran out of SGEs while reading */
#define PORT_CERR_PKT_PROT 11 /* DIR invalid in 1st PIO setup of ATAPI */
#define PORT_CERR_SGT_BOUNDARY 16 /* PLD ecode 00 - SGT not on qword boundary */
#define PORT_CERR_SGT_TGTABRT 17 /* PLD ecode 01 - target abort */
#define PORT_CERR_SGT_MSTABRT 18 /* PLD ecode 10 - master abort */
#define PORT_CERR_SGT_PCIPERR 19 /* PLD ecode 11 - PCI parity err while fetching SGT */
#define PORT_CERR_CMD_BOUNDARY 24 /* ctrl[15:13] 001 - PRB not on qword boundary */
#define PORT_CERR_CMD_TGTABRT 25 /* ctrl[15:13] 010 - target abort */
#define PORT_CERR_CMD_MSTABRT 26 /* ctrl[15:13] 100 - master abort */
#define PORT_CERR_CMD_PCIPERR 27 /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
#define PORT_CERR_XFR_UNDEF 32 /* PSD ecode 00 - undefined */
#define PORT_CERR_XFR_TGTABRT 33 /* PSD ecode 01 - target abort */
#define PORT_CERR_XFR_MSTABRT 34 /* PSD ecode 10 - master abort */
#define PORT_CERR_XFR_PCIPERR 35 /* PSD ecode 11 - PCI prity err during transfer */
#define PORT_CERR_SENDSERVICE 36 /* FIS received while sending service */
/* bits of PRB control field */
#define PRB_CTRL_PROTOCOL (1 << 0) /* override def. ATA protocol */
#define PRB_CTRL_PACKET_READ (1 << 4) /* PACKET cmd read */
#define PRB_CTRL_PACKET_WRITE (1 << 5) /* PACKET cmd write */
#define PRB_CTRL_NIEN (1 << 6) /* Mask completion irq */
#define PRB_CTRL_SRST (1 << 7) /* Soft reset request (ign BSY?) */
/* PRB protocol field */
#define PRB_PROT_PACKET (1 << 0)
#define PRB_PROT_TCQ (1 << 1)
#define PRB_PROT_NCQ (1 << 2)
#define PRB_PROT_READ (1 << 3)
#define PRB_PROT_WRITE (1 << 4)
#define PRB_PROT_TRANSPARENT (1 << 5)
/*
* Other constants
*/
#define SGE_TRM (1 << 31) /* Last SGE in chain */
#define SGE_LNK (1 << 30) /* linked list
Points to SGT, not SGE */
#define SGE_DRD (1 << 29) /* discard data read (/dev/null)
data address ignored */
#define SIL24_MAX_CMDS 31
/* host flags */
#define SIL24_COMMON_FLAGS ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | \
ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | \
ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY | \
ATA_FLAG_ACPI_SATA
#define SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24) /* IRQ loss errata on PCI-X */
#define IRQ_STAT_4PORTS 0xf
/* * Port request block (PRB) 32 bytes */
typedef struct sil24_prb
{
UINT16 ctrl;
UINT16 prot;
UINT32 rx_cnt;
UINT8 fis[6 * 4];
}SIL24_PRB;
/* * Scatter gather entry (SGE) 16 bytes */
typedef struct sil24_sge
{
UINT32 addrlow;
UINT32 addrhigh;
UINT32 cnt;
UINT32 flags;
}SIL24_SGE;
typedef struct sil24_sata_block {
SIL24_PRB prb;
SIL24_SGE sge[2];
}SIL24_SATA_BLOCK;
typedef struct sataParams
{
short config; /* general configuration */
short cylinders; /* number of cylinders */
short removcyl; /* number of removable cylinders */
short heads; /* number of heads */
short bytesTrack; /* number of unformatted bytes/track */
short bytesSec; /* number of unformatted bytes/sector */
short sectors; /* number of sectors/track */
short bytesGap; /* minimum bytes in intersector gap */
short bytesSync; /* minimum bytes in sync field */
short vendstat; /* number of words of vendor status */
char serial[20]; /* controller serial number */
short type; /* controller type */
short size; /* sector buffer size, in sectors */
short bytesEcc; /* ecc bytes appended */
char rev[8]; /* firmware revision */
char model[40]; /* model name */
short multiSecs; /* RW multiple support. bits 7-0 ia max secs */
short reserved48; /* reserved */
short capabilities; /* capabilities */
short reserved50; /* reserved */
short pioMode; /* PIO data transfer cycle timing mode */
short dmaMode; /* single word DMA data transfer cycle timing */
short valid; /* field validity */
short currentCylinders; /* number of current logical cylinders */
short currentHeads; /* number of current logical heads */
short currentSectors; /* number of current logical sectors / track */
short capacity0; /* current capacity in sectors */
short capacity1; /* current capacity in sectors */
short multiSet; /* multiple sector setting */
short sectors0; /* total number of user addressable sectors */
short sectors1; /* total number of user addressable sectors */
short singleDma; /* [62]single word DMA transfer */
short multiDma; /* [63]multi word DMA transfer */
short advancedPio; /* [64]flow control PIO transfer modes supported */
short cycletimeDma; /* minimum multiword DMA transfer cycle time */
short cycletimeMulti; /* recommended multiword DMA cycle time */
short cycletimePioNoIordy; /* min PIO transfer cycle time wo flow ctl */
short cycletimePioIordy; /* min PIO transfer cycle time w IORDY */
short reserved69; /* reserved */
short reserved70; /* reserved */
/* ATAPI */
short pktCmdRelTime; /* [71]Typical Time for Release after Packet */
short servCmdRelTime; /* [72]Typical Time for Release after SERVICE */
#if 0
short majorRevNum; /* [73] Major Revision Number (0|FFFF if no) */
short minorVersNum; /* [74] Minor Version Number (0|FFFF if no) */
#else
short reserved73[2];
#endif
short queuedepth; /* [75] 4-0 Maximum queue depth – 1*/
short reserved76[4]; /* 76-79 reserved */
short majorversNum; /* Major version number
0000h or FFFFh = device does not report version F 15 Reserved
F 14 Reserved for ATA/ATAPI-14
F 13 Reserved for ATA/ATAPI-13
F 12 Reserved for ATA/ATAPI-12
F 11 Reserved for ATA/ATAPI-11
F 10 Reserved for ATA/ATAPI-10
F 9 Reserved for ATA/ATAPI-9
F 8 Reserved for ATA/ATAPI-8
F 7 Reserved for ATA/ATAPI-7
F 6 1 = supports ATA/ATAPI-6
F 5 1 = supports ATA/ATAPI-5
F 4 1 = supports ATA/ATAPI-4
F 3 1 = supports ATA-3
X 2 Obsolete
X 1 Obsolete
F 0 Reserved*/
short minorVersNum; /* Minor version number
0000h or FFFFh = device does not report version
0001h-FFFEh = see 3.16.41*/
short commandSetSup1; /* [82] Command set supported*/
short commandSetSup2;
short commandSetExt; /* Command set/feature supported extension*/
short commandSetEnable1; /* Command set/feature enabled. */
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