os_cpu_a.s

提高μCOS-II在ARM上执行效率的几种方法》相应代码

; File: os_cpu_a.s
;
;            Copyright 2002 by Interniche Technologies Inc.  All rights reserved. 
;
;            ARM Specific code for ChronOS port to Samsung/ARM7 board.
;
; modify OSTickISR and OSIntCtxSw by zlin


;***********************************************
; include files
;***********************************************

	GET option.s
	GET memcfg.s
	GET 2410addr.s

	
	AREA	|subr|, CODE, READONLY

;**********************************************************
; export functions
;**********************************************************

	EXPORT	OSIntCtxSw
	EXPORT  OSTickISR
	EXPORT  EInt0Isr
	EXPORT	OS_TASK_SW
	EXPORT	OSStartHighRdy
	
	EXPORT  INTS_OFF
	EXPORT  INTS_ON

;**********************************************************
; IMPORT
; External symbols we need the addresses of
;**********************************************************
	IMPORT	OSTCBCur
	IMPORT	OSTCBHighRdy
	IMPORT	OSPrioCur
	IMPORT	OSPrioHighRdy
	IMPORT  OSRunning

	IMPORT	OSIntEnter
	IMPORT	OSTimeTick
	IMPORT	OSIntExit
	
	IMPORT  OSSemPost
	IMPORT  mysem
	IMPORT  Uart_SendUWord32

;**********************************************************
; valuable
;**********************************************************
SAVED_LR_IRQ		DCD 0
SAVED_LR_SVC		DCD 0
SAVED_SPSR		DCD 0
OSIntCtxSwFlag		DCD 0

    MACRO
$SetTimerCnt    SET_TIMER   
    MEND  

;**********************************************************
;			INTS_OFF
; mask off(set to 1) IRQ and FIQ
; return: r0 is the retrun value, and is IRQ of privous CSR
;**********************************************************
INTS_OFF
   mrs   r0, cpsr          ; mov csr to r0, current CSR
   mov   r1, r0            ; make a copy for masking
   orr   r1, r1, #0xC0     ; mask off int bits, 0xC0 crrespond to I and F bit(1 for disable)
   msr   CPSR_cxsf, r1     ; disable ints (IRQ and FIQ)
   and   r0, r0, #0x80     ; return FIQ bit from original CSR
   mov   pc,lr             ; return

;**********************************************************
;			INTS_ON
; mask on(set to 0) IRQ and FIQ
; return: void
;**********************************************************
INTS_ON
   mrs   r0, cpsr          ; current CSR
   bic   r0, r0, #0xC0     ; mask on ints
   msr   CPSR_cxsf, r0     ; enable ints (IRQ and FIQ)
   mov   pc,lr             ; return


;**********************************************************
;			OSTickISR & OSIntCtxSw
;**********************************************************


;**********************************************************
;			INT_PORT_METHOD 1
;**********************************************************

	[ INT_PORT_METHOD = 1
EInt0Isr
	SUB	lr,  lr, #4
	STMFD	sp!, {r0-r12, lr}	

	bl 		OSIntEnter
	
	; ClearPending(BIT_EINT0);
	LDR		r0,		=SRCPND
	LDR		r1,		=BIT_EINT0
	STR		r1,		[r0]
	LDR		r0,		=INTPND
	STR		r1,		[r0]
	
	; OSSemPost(mysem);
	LDR     r1,     =mysem
	LDR     r0,     [r1]
	BL      OSSemPost
	
	SET_TIMER  
	
	BL		OSIntExit
	
	LDR		r0,		=OSIntCtxSwFlag
	LDR		r1,		[r0]
	CMP		r1,		#1
	BEQ		_IntCtxSw
	
	LDMFD		sp!,	{r0-r12, pc}^

OSTickISR
	
	; lr - 4 will be the return address(pc). in all task stack we
	; get r0-r12, pc(lr_irq), cpsr(spsr_irq), but now sp_svc, lr_svc, spsr_svc
	; is not available.
	SUB	lr,  lr, #4
	STMFD	sp!, {r0-r12, lr}	
	
	bl 		OSIntEnter
	bl		OSTimeTick
	
	; ClearPending(BIT_TIMER0);
	LDR		r0,		=SRCPND
	LDR		r1,		=BIT_TIMER0
	STR		r1,		[r0]
	LDR		r0,		=INTPND
	STR		r1,		[r0]
	
	BL		OSIntExit
	
	LDR		r0,		=OSIntCtxSwFlag
	LDR		r1,		[r0]
	CMP		r1,		#1
	BEQ		_IntCtxSw
	
	LDMFD		sp!,	{r0-r12, pc}^

OSIntCtxSw

	LDR 	r0,	 	=OSIntCtxSwFlag 
	MOV 	r1,		#1
	STR 	r1, 		[r0]     
	MOV 	pc, 		lr 
    
_IntCtxSw
	;**********************************************************************
	; OSIntCtxSwFlag = false
	;**********************************************************************
	MOV		r1,		#0
	STR		r1,		[r0]

    ;**********************************************************************
    ; save information before leave irq mode
	;**********************************************************************

	;save spsr_irq
    MRS 	r4,	    spsr
    STR 	r4, 	SAVED_SPSR

	;load registers
    LDMFD 	sp!, 	{r0-r12, lr} 

	;save lr_irq, return address
    STR 	lr, 	SAVED_LR_IRQ 
    
	;**********************************************************************
	; change to svc
	;**********************************************************************

	MRS 	lr, 	cpsr
    ORR 	lr, 	lr,		#1 
    MSR 	cpsr_cxsf,	    lr 

    ;**********************************************************************
    ; empty a register for usage, here select the lr register
	;**********************************************************************

    ; save lr_svc
    STR 	lr, 	SAVED_LR_SVC

	;**********************************************************************
    ; push registers 
	;**********************************************************************

	;push lr_irq, is pc
    LDR 	lr, 	SAVED_LR_IRQ 
    STMFD 	sp!, 	{lr} 
        
	; push lr_svc is lr, push lr and r0-r12
	LDR 	lr, 	SAVED_LR_SVC 
    STMFD 	sp!, 	{r0-r12} 
    STMFD   sp!,    {lr}
        
	LDR 	r4, 	SAVED_SPSR
    STMFD 	sp!, 	{r4} 
    STMFD 	sp!, 	{r4} 
    
    B _OSCtxSw 

    ]   ;end of method 1

;**********************************************************
;			INT_PORT_METHOD 2
;**********************************************************

	[ INT_PORT_METHOD = 2	
EInt0Isr
	SUB	lr,  lr, #4
	STMFD	sp!, {r0-r12, lr}	

	bl 		OSIntEnter
	
	; ClearPending(BIT_EINT0);
	LDR		r0,		=SRCPND
	LDR		r1,		=BIT_EINT0
	STR		r1,		[r0]
	LDR		r0,		=INTPND
	STR		r1,		[r0]
	
	; OSSemPost(mysem);
	LDR     r1,     =mysem
	LDR     r0,     [r1]
	BL      OSSemPost
	
	SET_TIMER  
	
	BL		OSIntExit
	
	LDMFD		sp!,	{r0-r12, pc}^

OSTickISR
	; lr - 4 will be the return address(pc). in all task stack we
	; get r0-r12, pc(lr_irq), cpsr(spsr_irq), but now sp_svc, lr_svc, spsr_svc
	; is not available.
	SUB	lr,  lr, #4
	STMFD	sp!, {r0-r12, lr}	
	
	bl 		OSIntEnter
	bl		OSTimeTick
	
	; ClearPending(BIT_TIMER0);
	LDR		r0,		=SRCPND
	LDR		r1,		=BIT_TIMER0
	STR		r1,		[r0]
	LDR		r0,		=INTPND
	STR		r1,		[r0]
	
	BL		OSIntExit
	
	LDMFD		sp!,		{r0-r12, pc}^

OSIntCtxSw
    ;**********************************************************
    ;		adjust sp to just enter isr(after push registers)
    ;**********************************************************
	add     sp,	sp,	#0x10

    ;**********************************************************************
    ; save information before leave irq mode
	;**********************************************************************

	;save spsr_irq
    MRS 	r4,	    spsr
    STR 	r4, 	SAVED_SPSR

	;load registers
    LDMFD 	sp!, 	{r0-r12, lr} 

	;save lr_irq, return address
    STR 	lr, 	SAVED_LR_IRQ 
    
	;**********************************************************************
	; change to svc
	;**********************************************************************

	MRS 	lr, 	cpsr
    ORR 	lr, 	lr,		#1 
    MSR 	cpsr_cxsf,	    lr 

    ;**********************************************************************
    ; empty a register for usage, here select the lr register
	;**********************************************************************

    ; save lr_svc
    STR 	lr, 	SAVED_LR_SVC

	;**********************************************************************
    ; push registers 
	;**********************************************************************

	;push lr_irq, is pc
    LDR 	lr, 	SAVED_LR_IRQ 
    STMFD 	sp!, 	{lr}