pcilynx.h

Ieee1394驱动实现

#ifndef __PCILYNX_H__
#define __PCILYNX_H__


#define PCILYNX_DRIVER_NAME      "pcilynx"
#define PCILYNX_MAJOR            177

#define PCILYNX_MINOR_AUX_START  0
#define PCILYNX_MINOR_ROM_START  16
#define PCILYNX_MINOR_RAM_START  32

#define PCILYNX_MAX_REGISTER     0xfff
#define PCILYNX_MAX_MEMORY       0xffff

#define PCI_DEVICE_ID_TI_PCILYNX 0x8000
#define MAX_PCILYNX_CARDS        4
#define LOCALRAM_SIZE            4096

#define NUM_ISORCV_PCL           4
#define MAX_ISORCV_SIZE          2048
#define ISORCV_PER_PAGE          (PAGE_SIZE / MAX_ISORCV_SIZE)
#define ISORCV_PAGES             (NUM_ISORCV_PCL / ISORCV_PER_PAGE)

#define CHANNEL_LOCALBUS         0
#define CHANNEL_ASYNC_RCV        1
#define CHANNEL_ISO_RCV          2
#define CHANNEL_ASYNC_SEND       3
#define CHANNEL_ISO_SEND         4

#define PCILYNX_CONFIG_ROM_LENGTH   1024

typedef int pcl_t;

struct ti_lynx {
        int id; /* sequential card number */

        spinlock_t lock;

        struct pci_dev *dev;

        struct {
                unsigned reg_1394a:1;
                u32 vendor;
                u32 product;
        } phyic;

        enum { clear, have_intr, have_aux_buf, have_pcl_mem,
               have_1394_buffers, have_iomappings, is_host } state;

        /* remapped memory spaces */
        void __iomem *registers;
        void __iomem *local_rom;
        void __iomem *local_ram;
        void __iomem *aux_port;
	quadlet_t bus_info_block[5];

        /*
         * use local RAM of LOCALRAM_SIZE bytes for PCLs, which allows for
         * LOCALRAM_SIZE * 8 PCLs (each sized 128 bytes);
         * the following is an allocation bitmap
         */
        u8 pcl_bmap[LOCALRAM_SIZE / 1024];

	/* point to PCLs memory area if needed */
	void *pcl_mem;
        dma_addr_t pcl_mem_dma;

        /* PCLs for local mem / aux transfers */
        pcl_t dmem_pcl;

        /* IEEE-1394 part follows */
        struct hpsb_host *host;

        int phyid, isroot;
        int selfid_size;
        int phy_reg0;

        spinlock_t phy_reg_lock;

        pcl_t rcv_pcl_start, rcv_pcl;
        void *rcv_page;
        dma_addr_t rcv_page_dma;
        int rcv_active;

        struct lynx_send_data {
                pcl_t pcl_start, pcl;
                struct list_head queue;
                struct list_head pcl_queue; /* this queue contains at most one packet */
                spinlock_t queue_lock;
                dma_addr_t header_dma, data_dma;
                int channel;
        } async, iso_send;

        struct {
                pcl_t pcl[NUM_ISORCV_PCL];
                u32 stat[NUM_ISORCV_PCL];
                void *page[ISORCV_PAGES];
                dma_addr_t page_dma[ISORCV_PAGES];
                pcl_t pcl_start;
                int chan_count;
                int next, last, used, running;
                struct tasklet_struct tq;
                spinlock_t lock;
        } iso_rcv;

	u32 i2c_driven_state; /* the state we currently drive the Serial EEPROM Control register */
};

/* the per-file data structure for mem space access */
struct memdata {
        struct ti_lynx *lynx;
        int cid;
        atomic_t aux_intr_last_seen;
	/* enum values are the same as LBUS_ADDR_SEL_* values below */
        enum { rom = 0x10000, aux = 0x20000, ram = 0 } type;
};



/*
 * Register read and write helper functions.
 */
static inline void reg_write(const struct ti_lynx *lynx, int offset, u32 data)
{
        writel(data, lynx->registers + offset);
}

static inline u32 reg_read(const struct ti_lynx *lynx, int offset)
{
        return readl(lynx->registers + offset);
}

static inline void reg_set_bits(const struct ti_lynx *lynx, int offset,
                                u32 mask)
{
        reg_write(lynx, offset, (reg_read(lynx, offset) | mask));
}

static inline void reg_clear_bits(const struct ti_lynx *lynx, int offset,
                                  u32 mask)
{
        reg_write(lynx, offset, (reg_read(lynx, offset) & ~mask));
}



/* chip register definitions follow */

#define PCI_LATENCY_CACHELINE             0x0c

#define MISC_CONTROL                      0x40
#define MISC_CONTROL_SWRESET              (1<<0)

#define SERIAL_EEPROM_CONTROL             0x44

#define PCI_INT_STATUS                    0x48
#define PCI_INT_ENABLE                    0x4c
/* status and enable have identical bit numbers */
#define PCI_INT_INT_PEND                  (1<<31)
#define PCI_INT_FORCED_INT                (1<<30)
#define PCI_INT_SLV_ADR_PERR              (1<<28)
#define PCI_INT_SLV_DAT_PERR              (1<<27)
#define PCI_INT_MST_DAT_PERR              (1<<26)
#define PCI_INT_MST_DEV_TIMEOUT           (1<<25)
#define PCI_INT_INTERNAL_SLV_TIMEOUT      (1<<23)
#define PCI_INT_AUX_TIMEOUT               (1<<18)
#define PCI_INT_AUX_INT                   (1<<17)
#define PCI_INT_1394                      (1<<16)
#define PCI_INT_DMA4_PCL                  (1<<9)
#define PCI_INT_DMA4_HLT                  (1<<8)
#define PCI_INT_DMA3_PCL                  (1<<7)
#define PCI_INT_DMA3_HLT                  (1<<6)
#define PCI_INT_DMA2_PCL                  (1<<5)
#define PCI_INT_DMA2_HLT                  (1<<4)
#define PCI_INT_DMA1_PCL                  (1<<3)
#define PCI_INT_DMA1_HLT                  (1<<2)
#define PCI_INT_DMA0_PCL                  (1<<1)
#define PCI_INT_DMA0_HLT                  (1<<0)
/* all DMA interrupts combined: */
#define PCI_INT_DMA_ALL                   0x3ff

#define PCI_INT_DMA_HLT(chan)             (1 << (chan * 2))
#define PCI_INT_DMA_PCL(chan)             (1 << (chan * 2 + 1))

#define LBUS_ADDR                         0xb4
#define LBUS_ADDR_SEL_RAM                 (0x0<<16)
#define LBUS_ADDR_SEL_ROM                 (0x1<<16)
#define LBUS_ADDR_SEL_AUX                 (0x2<<16)
#define LBUS_ADDR_SEL_ZV                  (0x3<<16)

#define GPIO_CTRL_A                       0xb8
#define GPIO_CTRL_B                       0xbc
#define GPIO_DATA_BASE                    0xc0

#define DMA_BREG(base, chan)              (base + chan * 0x20)
#define DMA_SREG(base, chan)              (base + chan * 0x10)

#define DMA0_PREV_PCL                     0x100
#define DMA1_PREV_PCL                     0x120
#define DMA2_PREV_PCL                     0x140
#define DMA3_PREV_PCL                     0x160
#define DMA4_PREV_PCL                     0x180
#define DMA_PREV_PCL(chan)                (DMA_BREG(DMA0_PREV_PCL, chan))

#define DMA0_CURRENT_PCL                  0x104
#define DMA1_CURRENT_PCL                  0x124
#define DMA2_CURRENT_PCL                  0x144
#define DMA3_CURRENT_PCL                  0x164
#define DMA4_CURRENT_PCL                  0x184
#define DMA_CURRENT_PCL(chan)             (DMA_BREG(DMA0_CURRENT_PCL, chan))

#define DMA0_CHAN_STAT                    0x10c
#define DMA1_CHAN_STAT                    0x12c
#define DMA2_CHAN_STAT                    0x14c
#define DMA3_CHAN_STAT                    0x16c
#define DMA4_CHAN_STAT                    0x18c
#define DMA_CHAN_STAT(chan)               (DMA_BREG(DMA0_CHAN_STAT, chan))
/* CHAN_STATUS registers share bits */
#define DMA_CHAN_STAT_SELFID              (1<<31)
#define DMA_CHAN_STAT_ISOPKT              (1<<30)
#define DMA_CHAN_STAT_PCIERR              (1<<29)
#define DMA_CHAN_STAT_PKTERR              (1<<28)
#define DMA_CHAN_STAT_PKTCMPL             (1<<27)
#define DMA_CHAN_STAT_SPECIALACK          (1<<14)


#define DMA0_CHAN_CTRL                    0x110
#define DMA1_CHAN_CTRL                    0x130
#define DMA2_CHAN_CTRL                    0x150
#define DMA3_CHAN_CTRL                    0x170
#define DMA4_CHAN_CTRL                    0x190
#define DMA_CHAN_CTRL(chan)               (DMA_BREG(DMA0_CHAN_CTRL, chan))
/* CHAN_CTRL registers share bits */
#define DMA_CHAN_CTRL_ENABLE              (1<<31)
#define DMA_CHAN_CTRL_BUSY                (1<<30)