syslib.c

vxworks MPC8541 BSP

    switch (regVal)
	{
	case 0:
	default:
	    speUnitPresent = OK;
	    break;
	}      /* switch  */

    return (speUnitPresent);
    }
#endif  /* INCLUDE_SPE */

/******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string.
*/

char * sysModel (void)
    {
    UINT device;

    device = *M85XX_SVR(CCSBAR);

    if ((device & 0xffff0000) == 0x80700000)
        return(SYS_MODEL_8560);

    if ((device & 0xffff0000) == 0x80300000)
        return(SYS_MODEL_8540);

    if ((device & 0xffff0000) == 0x80790000)
        return(SYS_MODEL_8555);

    if ((device & 0xffff0000) == 0x807a0000)
        return(SYS_MODEL_8541);

    device = *M85XX_PVR(CCSBAR);
    if ((device & 0xffff0000) == 0x80200000)
        return (SYS_MODEL_E500);

    return (SYS_MODEL_UNKNOWN);

    }

/******************************************************************************
*
* sysBspRev - return the bsp version with the revision eg 1.0/<x>
*
* This function returns a pointer to a bsp version with the revision.
* for eg. 1.0/<x>. BSP_REV defined in config.h is concatanated to
* BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }

UINT32 sysClkFreqGet
    (
    void
    )
    {
    UINT32  sysClkFreq;
    UINT32 e500Ratio,platRatio;
 

    platRatio = M85XX_PORPLLSR_PLAT_RATIO(CCSBAR); 
    
    if ((platRatio>=MAX_VALUE_PLAT_RATIO)||(platRatioTable[platRatio][0]==0))
	return ERROR;

    sysClkFreq = ((UINT32)(OSCILLATOR_FREQ * platRatioTable[platRatio][0]))>>((UINT32)platRatioTable[platRatio][1]);

    e500Ratio = M85XX_PORPLLSR_E500_RATIO(CCSBAR);
    coreFreq = ((UINT32)(sysClkFreq * e500RatioTable[e500Ratio][0]))>>((UINT32)e500RatioTable[e500Ratio][1]);


    return sysClkFreq;
    }

/******************************************************************************
  *
  * sysCpmFreqGet - Determines the CPM Operating Frequency
  *
  * From page 9-2 Rev. 0  MPC8260  PowerQUICC II User's Manual
  *
  * RETURNS: CPM clock frequency for the current MOD_CK and MOD_CK_H settings  
  */


UINT32 sysCpmFreqGet
    (
    void
    )
    {
    UINT32 sysClkFreq = sysClkFreqGet();
    return  (sysClkFreq);

    }

/******************************************************************************
*
* sysBaudClkFreq - Obtains frequency of the BRG_CLK in HZ
*
* From page 9-5 in Rev. 0 MPC8260 PowerQUICC II User's Manual
*
*     baud clock = 2*cpm_freq/2^2*(DFBRG+1) where DFBRG = 01
*                = 2*cpm_freq/16
*
* RETURNS: frequency of the BRG_CLK in HZ
*/

UINT32 sysBaudClkFreq
    (
    void
    )
    {
    UINT32 cpmFreq = sysCpmFreqGet();

    if (cpmFreq == (UINT32)ERROR)
        return ERROR;
    else
        return cpmFreq*2/16;
    }

/******************************************************************************
 *
 * sysHwMemInit - initialize and configure system memory.
 *
 * This routine is called before sysHwInit(). It performs memory auto-sizing
 * and updates the system's physical regions table, `sysPhysRgnTbl'. It may
 * include the code to do runtime configuration of extra memory controllers.
 *
 * NOTE: This routine should not be called directly by the user application.  It
 * cannot be used to initialize interrupt vectors.
 *
 * RETURNS: N/A
 */

void sysHwMemInit (void)
    {
    /* Call sysPhysMemTop() to do memory autosizing if available */

    sysPhysMemTop ();

    }

/******************************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes various feature of the MPC8260 ADS board. It sets up
* the control registers, initializes various devices if they are present.
*
* NOTE: This routine should not be called directly by the user.
*
* RETURNS: NA
*/

void sysHwInit (void)
    {

#ifdef INCLUDE_CPM
    UINT32 immrVal = vxImmrGet();
    memset((char*)(CCSBAR+0x80000),(int)0,0x1000);
    m82xxDpramLibInit();


    /* Zero IO Port registers */
    /* reset the parallel ports */

    * M8260_IOP_PADIR(immrVal) = 0x00000000;
    * M8260_IOP_PAPAR(immrVal) = 0x00000000;
    * M8260_IOP_PASO(immrVal) = 0x00000000;
    * M8260_IOP_PAODR(immrVal) = 0x00000000;
    * M8260_IOP_PADAT(immrVal) = 0x00000000;

    * M8260_IOP_PBDIR(immrVal) = 0x00000000;
    * M8260_IOP_PBPAR(immrVal) = 0x00000000;
    * M8260_IOP_PBSO(immrVal) = 0x00000000;
    * M8260_IOP_PBODR(immrVal) = 0x00000000;
    * M8260_IOP_PBDAT(immrVal) = 0x00000000;

    * M8260_IOP_PCDIR(immrVal) = 0x00000000;
    * M8260_IOP_PCPAR(immrVal) = 0x00000000;
    * M8260_IOP_PCSO(immrVal) = 0x00000000;
    * M8260_IOP_PCODR(immrVal) = 0x00000000;
    * M8260_IOP_PCDAT(immrVal) = 0x00000000;

    * M8260_IOP_PDDIR(immrVal) = 0x00000000;
    * M8260_IOP_PDPAR(immrVal) = 0x00000000;
    * M8260_IOP_PDSO(immrVal) = 0x00000000;
    * M8260_IOP_PDODR(immrVal) = 0x00000000;
    * M8260_IOP_PDDAT(immrVal) = 0x00000000;

#endif

    /* Disable L1 Icache */
    sysL1Csr1Set(vxL1CSR1Get() & ~0x1);

    /* Enable machine check pin */
    vxHid0Set(HID0_MCP|vxHid0Get());

    /* enable time base for delay use before DEC interrupt is setup */
    vxHid0Set(vxHid0Get() | _PPC_HID0_TBEN);

    sysTimerClkFreq = sysClkFreqGet()>>3 /* Clock div is 8 */;

#ifdef INCLUDE_AUX_CLK
    sysAuxClkRateSet(127);
#endif

#ifdef INCLUDE_CACHE_SUPPORT
    sysL1CacheQuery(); 
#endif /* INCLUDE_CACHE_SUPPORT */

    /* Initialise L2CTL register */
    vxL2CTLSet(0x28000000,M85XX_L2CTL(CCSBAR));

    /* Need to setup static TLB entries for bootrom or any non-MMU 
     * enabled images */

    mmuE500TlbDynamicInvalidate();
    mmuE500TlbStaticInvalidate();
    mmuE500TlbStaticInit(sysStaticTlbDescNumEnt, &sysStaticTlbDesc[0], TRUE);

#if (!defined(INCLUDE_MMU_BASIC) && !defined(INCLUDE_MMU_FULL))
    mmuPpcIEnabled=TRUE;
    mmuPpcDEnabled=TRUE;
#else /* !defined(INCLUDE_MMU_BASIC) && !defined(INCLUDE_MMU_FULL) */
    if (inFullVxWorksImage==FALSE)
	{
	mmuPpcIEnabled=TRUE;
	mmuPpcDEnabled=TRUE;
	}
    /* Enable I Cache if instruction mmu disabled */ 
#if (defined(USER_I_CACHE_ENABLE) && !defined(USER_I_MMU_ENABLE))
    mmuPpcIEnabled=TRUE;
#endif /* (defined(USER_I_CACHE_ENABLE) && !defined(USER_I_MMU_ENABLE)) */

#endif /* !defined(INCLUDE_MMU_BASIC) && !defined(INCLUDE_MMU_FULL) */

#ifdef INCLUDE_SCC_SERIAL
    * M85XX_CPM_SCCR(CCSBAR) = BRGCLK_DIV_FACTOR;
#endif

    /* set DPPC in SIUMCR to 10 so that timer is enabled (TBEN) */

    /* reset the Communications Processor */
#ifdef INCLUDE_CPM
    *M8260_CPCR(CCSBAR + 0x80000) = 0x80010000;
    baudRateGenClk = sysBaudClkFreq();
#endif

#if (defined(INCLUDE_L2_CACHE) && defined(INCLUDE_CACHE_SUPPORT))
    vxHid1Set(HID1_ABE); /* Address Broadcast enable */
    sysL2CacheInit();
#endif /* INCLUDE_L2_CACHE  && INCLUDE_CACHE_SUPPORT*/

    vxHid1Set(vxHid1Get()| HID1_ASTME); /* Address Stream Enable */

    /* Initialize the Embedded Programmable Interrupt Controller */

    sysEpicInit();

#ifdef INCLUDE_DUART
    sysDuartHwInit ();
#endif

#ifdef INCLUDE_SCC_SERIAL
    sysSerialHwInit();
#endif

    /* 060701 lyf add */
    dbgSerInit();   /* Initialize the SIO */
    /*dbgSerOutstr("serial port ok");*/

    b_getMachineType();
    /* end lyf add */

    /* Get the Baud Rate Generator Clock  frequency */

#ifdef INCLUDE_PCI

    /* config pci */

    if (pciConfigLibInit (PCI_MECHANISM_0,(ULONG) sysPciConfigRead,
			  (ULONG) sysPciConfigWrite,(ULONG) sysPciSpecialCycle) != OK)
        {
        sysToMonitor (BOOT_NO_AUTOBOOT);  /* BAIL */
        }

    /*  Initialize PCI interrupt library. */

    if ((pciIntLibInit ()) != OK)
        {
        sysToMonitor (BOOT_NO_AUTOBOOT);
        }

    if (*((char*)PCI_AUTO_CONFIG_ADRS) == FALSE)
        {
	mot85xxBridgeInit();
/*lint -e774*/
        if (PCI_CFG_TYPE == PCI_CFG_AUTO)
            sysPciAutoConfig();
/*lint +e774*/
        *((char*)PCI_AUTO_CONFIG_ADRS) = TRUE;
	}

#endif /* INCLUDE_PCI */
     
#ifdef INCLUDE_MOT_FCC_END
    sysFccEnetDisable (immrVal, 2);
#endif /* INCLUDE_MOT_FCC_END */

#ifdef INCLUDE_FEI_END
    sys557PciInit();
#endif  /* INCLUDE_FEI_END */

#ifdef INCLUDE_BCM56504
    sysBcmPciInit ();
#endif /* INCLUDE_BCM56504 */

    /*
     * The power management mode is initialized here. Reduced power mode
     * is activated only when the kernel is iddle (cf vxPowerDown).
     * Power management mode is selected via vxPowerModeSet().
     * DEFAULT_POWER_MGT_MODE is defined in config.h.
     */

#if defined(INCLUDE_L2_SRAM) 
#if (defined(INCLUDE_L2_CACHE) && defined(INCLUDE_CACHE_SUPPORT))
    sysL2SramEnable(TRUE);
#elif (defined(INCLUDE_L2_SRAM))
    sysL2SramEnable(FALSE);
#endif
#endif

    CACHE_PIPE_FLUSH();

    vxPowerModeSet (DEFAULT_POWER_MGT_MODE);

    SYS_LED_RUN(YEL_ON);

    sysBdcsInit ();
    }

#ifdef INCLUDE_L2_SRAM
/*************************************************************************
 *
 * sysL2SramEnable - Enables L2SRAM if L2SRAM only or initialises blk 
 * size etc and leaves the rest to L2 cache code
 *
 * RETURNS: N/A
 */
LOCAL void sysL2SramEnable(BOOL both)
    {
    volatile int l2CtlVal;
  
    /* if INCLUDE_L2_CACHE and CACHE_SUPPORT */
    /* if ((L2_SRAM_SIZE + L2_CACHE_SIZE) > l2Siz) */
    /* Setup Windows for L2SRAM */    
    *(M85XX_L2SRBAR0(CCSBAR)) = (UINT32)(L2SRAM_ADDR & M85XX_L2SRBAR_ADDR_MSK); 
    /* Get present value */
    l2CtlVal = vxL2CTLGet(M85XX_L2CTL(CCSBAR));

    /* Disable L2CTL initially to allow changing of block size */
    l2CtlVal&=(~M85XX_L2CTL_L2E_MSK);
    vxL2CTLSet(l2CtlVal,M85XX_L2CTL(CCSBAR));
    l2CtlVal &= ~M85XX_L2CTL_L2BLKSIZ_MSK;
    l2CtlVal &= ~M85XX_L2CTL_L2SRAM_MSK;

    if (both == TRUE)
	{
	/* Setup size of SRAM */
	l2CtlVal |= (L2SIZ_128KB << M85XX_L2CTL_L2BLKSIZ_BIT) | 
	  (0x2 << M85XX_L2CTL_L2SRAM_BIT);
	}
    else
	{
	l2CtlVal |= (L2SIZ_256KB << M85XX_L2CTL_L2BLKSIZ_BIT) | 
	  (0x1 << M85XX_L2CTL_L2SRAM_BIT);
	}

    /* Setup L2CTL for SRAM */
    vxL2CTLSet(l2CtlVal,M85XX_L2CTL(CCSBAR));

    if (both == FALSE)
	{
	/* This is done here so L2SRAM is set before enable */
	l2CtlVal |= M85XX_L2CTL_L2E_MSK; /* No cache so go ahead and enable */
	/* Enable L2CTL for SRAM */
	vxL2CTLSet(l2CtlVal,M85XX_L2CTL(CCSBAR));
	}

    }
#endif /* INCLUDE_L2_SRAM */

/**************************************************************************
*
* sysPhysMemTop - get the address of the top of physical memory
*
* This routine returns the address of the first missing byte of memory,
* which indicates the top of memory.
*
* RETURNS: The address of the top of physical memory.
*
* SEE ALSO: sysMemTop()
*/

char * sysPhysMemTop (void)
    {
    LOCAL char * physTop = NULL;

    if (physTop == NULL)
	{
	physTop = (char *)(LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE);
	}

    return (physTop) ;
    }

/***************************************************************************
*
* sysMemTop - get the address of the top of VxWorks memory
*
* This routine returns a pointer to the first byte of memory not
* controlled or used by VxWorks.
*
* The user can reserve memory space by defining the macro USER_RESERVED_MEM
* in config.h.  This routine returns the address of the reserved memory
* area.  The value of USER_RESERVED_MEM is in bytes.
*
* RETURNS: The address of the top of VxWorks memory.
*/

char * sysMemTop (void)
    {
    LOCAL char * memTop = NULL;

    if (memTop == NULL)
    {
#ifdef __BOOTROM__
        memTop = sysPhysMemTop () - BOOT_RESERVED_MEM - TRACE_BUF_SIZE;
#else
        /*memTop = sysPhysMemTop () - USER_RESERVED_MEM;*/
        memTop = (char *)BSP_MEM_SIZE;
#endif /* __BOOTROM__ */

        }

    return memTop;
    }

/**************************************************************************
*
* sysToMonitor - transfer control to the ROM monitor
*
* This routine transfers control to the ROM monitor.  Normally, it is called
* only by reboot()--which services ^X--and bus errors at interrupt level.
* However, in some circumstances, the user may wish to introduce a
* <startType> to enable special boot ROM facilities.
*
* RETURNS: Does not return.
*/

STATUS sysToMonitor
    (
    int startType	/* parameter passed to ROM to tell it how to boot */
    )
    {
    FUNCPTR pRom = (FUNCPTR) (ROM_TEXT_ADRS + 4);	/* Warm reboot */

    intLock();

#ifdef INCLUDE_BRANCH_PREDICTION
    disableBranchPrediction();
#endif /* INCLUDE_BRANCH_PREDICTION */

#ifdef INCLUDE_CACHE_SUPPORT
    cacheDisable(INSTRUCTION_CACHE);
    cacheDisable(DATA_CACHE);
#endif
    sysClkDisable();

#ifdef INCLUDE_AUX_CLK
    sysAuxClkDisable();
#endif

    vxMsrSet (0);                     /* Let bootrom re-initialise */

    (*pRom) (startType);	/* jump to bootrom entry point */

    return (OK);	/* in case we ever continue from ROM monitor */
    }

/******************************************************************************
*
* sysHwInit2 - additional system configuration and initialization
*
* This routine connects system interrupts and does any additional
* configuration necessary.
*
* RETURNS: NA
*/

void sysHwInit2 (void)
    {

    excIntConnect ((VOIDFUNCPTR *) _EXC_OFF_DECR,
		   (VOIDFUNCPTR) sysClkInt);

    sysClkEnable();

#ifdef INCLUDE_AUX_CLK
    excIntConnect ((VOIDFUNCPTR *) _EXC_OFF_FIT, (VOIDFUNCPTR) sysAuxClkInt);
#endif

    /* This was previously reqd for errata workaround #29, the workaround 
     * has been replaced with patch for spr99776, so it now serves as an 
     * example of implementing an l1 instruction parity handler 
     */  
#ifdef INCLUDE_L1_ICACHE_PARITY_ERROR_HANDLER
    memcpy((void*)_EXC_OFF_END,(void *)jumpIParity,sizeof(INSTR));
    sysIvor1Set(_EXC_OFF_END);

    cacheTextUpdate((void*)jumpIParity,sizeof(INSTR));

    cacheDisable(INSTRUCTION_CACHE);
    vxL1CSR1Set(vxL1CSR1Get()|_PPC_L1CSR_CPE);
    cacheEnable(INSTRUCTION_CACHE);
#endif /* INCLUDE_L1_ICACHE_PARITY_ERROR_HANDLER */

    /* intialize the EPIC interrupts */
    sysEpicIntrInit ();

#ifdef INCLUDE_CPM 
    sysCpmHwInit2();
#endif
    /* initialize serial interrupts */

#if (defined(INCLUDE_DUART) || defined(INCLUDE_SCC_SERIAL))
    sysSerialHwInit2 ();
#endif /* INCLUDE_DUART | INCLUDE_SCC_SERIAL */

#if     defined (INCLUDE_SPE)