m85xxmemc.h

vxworks MPC8541 BSP

/* m85xxMemc.h - Motorola MPC85xx Memory Controller header file */

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,24mar06,lzq  created.
*/

/*
 * This file contains constants for the Memory Controller in the 
 * Motorola MPC85xx PowerQUICC III integrated Communications Processor
 */

#ifndef __INCm85xxMemch
#define __INCm85xxMemch

#ifdef __cplusplus
    extern "C" {
#endif
    
#ifndef M8260ABBREVIATIONS
#define M8260ABBREVIATIONS

#ifdef  _ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
typedef volatile UCHAR VCHAR;   /* shorthand for volatile UCHAR */
typedef volatile INT32 VINT32; /* volatile unsigned word */
typedef volatile INT16 VINT16; /* volatile unsigned halfword */
typedef volatile INT8 VINT8;   /* volatile unsigned byte */
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
typedef volatile UINT8 VUINT8;   /* volatile unsigned byte */
#define CAST(x) (x)
#endif  /* _ASMLANGUAGE */

#endif /* M8260ABBREVIATIONS */

/* Local Access Windows Regster Offsets from CCSBAR */
/* LAWBARx 
 * 0-11 Reserved - read 0
 * 12-31 Base address - Most significan 20 bits 
 *
 * LAWARx
 * 0   Enable window
 * 1-7 Reserved
 * 8-11 Target interface - 0000 PCI/PCI-X
 *                       - 0001 -> 0011 Reserved
 *                       - 0100 Local Bus memory controller eg SDRAM/L2SRAM
 *                       - 0101 -> 1011 Reserved
 *                       - 1100 Rapid IO
 *                       - 1101 -> 1110 Reserved
 *                       - 1111 DDR SDRAM
 * 12-25 Reserved - read 0
 * 26-31 Size of Window  - min 001011 -> 4KBytes
 *                       step power of 2
 *                       - max 011110 -> 2 Gbytes
 */

/* Used for DDR SDRAM */
#define  M85XX_LAWBAR0(base)        (CAST(VUINT32 *)((base) + 0xc08))
#define  M85XX_LAWAR0(base)         (CAST(VUINT32 *)((base) + 0xc10))
/* Used for LBC SDRAM */
#define  M85XX_LAWBAR1(base)        (CAST(VUINT32 *)((base) + 0xc28))
#define  M85XX_LAWAR1(base)         (CAST(VUINT32 *)((base) + 0xc30))
/* Not Used   */
#define  M85XX_LAWBAR2(base)        (CAST(VUINT32 *)((base) + 0xc48))
#define  M85XX_LAWAR2(base)         (CAST(VUINT32 *)((base) + 0xc50))
/* Used for PCI */
#define  M85XX_LAWBAR3(base)        (CAST(VUINT32 *)((base) + 0xc68))
#define  M85XX_LAWAR3(base)         (CAST(VUINT32 *)((base) + 0xc70))
/* Flash */
#define  M85XX_LAWBAR4(base)        (CAST(VUINT32 *)((base) + 0xc88))
#define  M85XX_LAWAR4(base)         (CAST(VUINT32 *)((base) + 0xc90))
/* Not Used */
#define  M85XX_LAWBAR5(base)        (CAST(VUINT32 *)((base) + 0xcA8))
#define  M85XX_LAWAR5(base)         (CAST(VUINT32 *)((base) + 0xcB0))
/* Not Used */
#define  M85XX_LAWBAR6(base)        (CAST(VUINT32 *)((base) + 0xcc8))    
#define  M85XX_LAWAR6(base)         (CAST(VUINT32 *)((base) + 0xcd0))
/* Not Used */
#define  M85XX_LAWBAR7(base)        (CAST(VUINT32 *)((base) + 0xce8))
#define  M85XX_LAWAR7(base)         (CAST(VUINT32 *)((base) + 0xcf0))

#define  LAWBAR_ADRS_SHIFT  12
#define  LAWAR_ENABLE       0x80000000
#define  LAWAR_TGTIF_PCI       0x00000000
#define  LAWAR_TGTIF_PCI2      0x00100000
#define  LAWAR_TGTIF_LBC       0x00400000
#define  LAWAR_TGTIF_RAPIDIO   0x00c00000
#define  LAWAR_TGTIF_DDRSDRAM  0x00F00000

/* LAWAR SIZE Settings */ 
#define  LAWAR_SIZE_4KB     0x0000000B
#define  LAWAR_SIZE_8KB     0x0000000C
#define  LAWAR_SIZE_16KB    0x0000000D
#define  LAWAR_SIZE_32KB    0x0000000E
#define  LAWAR_SIZE_64KB    0x0000000F
#define  LAWAR_SIZE_128KB   0x00000010
#define  LAWAR_SIZE_256KB   0x00000011
#define  LAWAR_SIZE_512KB   0x00000012
#define  LAWAR_SIZE_1MB     0x00000013
#define  LAWAR_SIZE_2MB     0x00000014
#define  LAWAR_SIZE_4MB     0x00000015
#define  LAWAR_SIZE_8MB     0x00000016
#define  LAWAR_SIZE_16MB    0x00000017
#define  LAWAR_SIZE_32MB    0x00000018
#define  LAWAR_SIZE_64MB    0x00000019
#define  LAWAR_SIZE_128MB   0x0000001A
#define  LAWAR_SIZE_256MB   0x0000001B
#define  LAWAR_SIZE_512MB   0x0000001C
#define  LAWAR_SIZE_1GB     0x0000001D
#define  LAWAR_SIZE_2GB     0x0000001E

/* Local Bus Controller (LBC) Registers */
/* BRx 0-16 Base Address
 *     17-18 Extended Base Address 
 *     19-20 Port Size - 00 reserved
 *                     - 01 8bit
 *                     - 10 16bit
 *                     - 11 32bit
 *     21-22 Data Error Correction
 *                     - 00 reserved
 *                     - 01 Normal parity 
 *                     - 10 RMW parity generation (32-bit)
 *                     - 11 reserved
 *     23    Write Protect
 *     24-26 Machine Select = 000 GPCM
 *                          - 001->010 reserved
 *                          - 011 SDRAM
 *                          - 100->110 UPMA->UPMC
 *                          - 111 reserved
 *     28-29 Atomic Access  - 00 No atomic access
 *                          - 01 Read-after-write
 *                          - 10 Write-after-read
 *                          - 11 reserved
 *     31    Valid     
 *      
 * ORx for SDRAM
 *     0-16  Address mask 
 *     17-18 Extended address mask
 *     19-21 Column address lines - 000->111 7->14
 *     23-25 Number of row address lines - 000->110 9->15
 *                                       - 111 Reserved
 *     26    Page mode select
 *     31    External address latch delay 
 *
 * ORx for GPCM Mode
 *     0-16  Address mask 
 *     17-18 Extended address mask
 *     19    Buffer Control Disable
 *     20    Chip select negation
 *     21-22 Addres to chip select setup
 *     23    Extra Address to chip select setup
 *     24-27 Cycle length in Bus clocks - 0000->1111 0->15 wait states
 *     28    External address termination
 *     29    Timing relaxed
 *     30    Extended hold time for read access
 *     31    External address latch delay  
 */


#define  M85XX_BR0(base)         (CAST(VUINT32 *)((base) + 0x5000))
#define  M85XX_OR0(base)         (CAST(VUINT32 *)((base) + 0x5004))
#define  M85XX_BR1(base)         (CAST(VUINT32 *)((base) + 0x5008))
#define  M85XX_OR1(base)         (CAST(VUINT32 *)((base) + 0x500c))
#define  M85XX_BR2(base)         (CAST(VUINT32 *)((base) + 0x5010))
#define  M85XX_OR2(base)         (CAST(VUINT32 *)((base) + 0x5014))
#define  M85XX_BR3(base)         (CAST(VUINT32 *)((base) + 0x5018))
#define  M85XX_OR3(base)         (CAST(VUINT32 *)((base) + 0x501c))
#define  M85XX_BR4(base)         (CAST(VUINT32 *)((base) + 0x5020))
#define  M85XX_OR4(base)         (CAST(VUINT32 *)((base) + 0x5024))
#define  M85XX_BR5(base)         (CAST(VUINT32 *)((base) + 0x5028))
#define  M85XX_OR5(base)         (CAST(VUINT32 *)((base) + 0x502C))
#define  M85XX_BR6(base)         (CAST(VUINT32 *)((base) + 0x5030))
#define  M85XX_OR6(base)         (CAST(VUINT32 *)((base) + 0x5034))
#define  M85XX_BR7(base)         (CAST(VUINT32 *)((base) + 0x5038))
#define  M85XX_OR7(base)         (CAST(VUINT32 *)((base) + 0x503C))

#define  M85XX_MAR(base)         (CAST(VUINT32 *)((base) + 0x5068))
#define  M85XX_MAMR(base)         (CAST(VUINT32 *)((base) + 0x5070))
#define  M85XX_MBMR(base)         (CAST(VUINT32 *)((base) + 0x5074))
#define  M85XX_MCMR(base)         (CAST(VUINT32 *)((base) + 0x5078))
#define  M85XX_MRTPR(base)         (CAST(VUINT32 *)((base) + 0x5084))
#define  MRTPR_PTP_MASK 0xff000000
#define  MRTPR_PTP_WRITE(x)   ( (x << 24) & MRTPR_PTP_MASK)
#define  M85XX_MDR(base)         (CAST(VUINT32 *)((base) + 0x5088))

#define  M85XX_LSDMR(base)         (CAST(VUINT32 *)((base) + 0x5094))
#define  LSDMR_RFEN     0x40000000 /* Refresh Enable */
/* LSDMR OP - 000 Normal operation
 *          - 001 Auto Refresh  (Initialization)
 *          - 010 Self Refresh
 *          - 011 Mode Register Write (Initialization)
 *          - 100 Precharge Bank
 *          - 101 Precharge all banks (Initialization)
 *          - 110 Activate Bank
 *          - 111 Read/Write without valid transfer
 */      
#define  LSDMR_OP_MASK  0x38000000
#define  LSDMR_OP_SHIFT(x) ((x << 27) & LSDMR_OP_MASK)
/* Bank Select Multiplexed address line - 000 lines 12:13
 *                                      - 001       13:14
 *                                      - 010       14:15
 *                                      - 011       15:16
 *                                      - 100       16:17
 *                                      - 101       17:18
 *                                      - 110       18:19
 *                                      - 111       19:20
 */
#define  LSDMR_BSMA_MASK 0x00E00000
#define  LSDMR_BSMA_SHIFT(x) ((x << 23) & LSDMR_BSMA_MASK)
/* RFCR Refresh recovery 000 - reserved
 *                       001->110 - 3->8 clocks
 *                       111 - 16 clocks
 */
#define  LSDMR_RFCR_MASK 0x00038000
#define  LSDMR_RFCR_SHIFT(x) ((x << 15) & LSDMR_RFCR_MASK)
/* Incomplete LSDMR definitions */


#define  M85XX_LURT(base)         (CAST(VUINT32 *)((base) + 0x50A0))
#define  M85XX_LSRT(base)         (CAST(VUINT32 *)((base) + 0x50A4))
#define  M85XX_LTESR(base)         (CAST(VUINT32 *)((base) + 0x50B0))
#define  M85XX_LTEDR(base)         (CAST(VUINT32 *)((base) + 0x50B4))
#define  M85XX_LTEIR(base)         (CAST(VUINT32 *)((base) + 0x50B8))
#define  M85XX_LTEATR(base)         (CAST(VUINT32 *)((base) + 0x50BC))
#define  M85XX_LTEAR(base)         (CAST(VUINT32 *)((base) + 0x50C0))

/* LBC Clock Configuration */
#define  M85XX_LBCR(base)         (CAST(VUINT32 *)((base) + 0x50D0))
#define  M85XX_LCRR(base)         (CAST(VUINT32 *)((base) + 0x50D4))


/* ECM Registers */
#define ECM_OFFSET 0x1000
#define ECMBA (CCSBAR | ECM_OFFSET)

/* Offsets for DDR registers */
#define DDR_OFFSET 0x2000
#define DDRBA      (CCSBAR | DDR_OFFSET)

#define CS0_BNDS   0x000
#define CS1_BNDS   0x008
#define CS2_BNDS   0x010
#define CS3_BNDS   0x018
#define CS0_CONFIG 0x080
#define CS1_CONFIG 0x084
#define CS2_CONFIG 0x088
#define CS3_CONFIG 0x08C
#define TIMING_CFG_1 0x108
#define TIMING_CFG_2 0x10C
#define DDR_SDRAM_CFG 0x110
#define DDR_SDRAM_MODE_CFG 0x118
#define DDR_SDRAM_INTERVAL 0x124
#define DDR_SDRAM_CLK_CNTL 0x130
#define DDR_DATA_ERR_INJECT_HI 0xe00
#define DDR_DATA_ERR_INJECT_LO 0xe04
#define DDR_ECC_ERR_INJECT 0xe08
#define DDR_CAPTURE_DATA_HI 0xe20
#define DDR_CAPTURE_DATA_LO 0xe24
#define DDR_CAPTURE_ECC 0xe28
#define DDR_ERR_DETECT 0xe40
#define DDR_ERR_DISABLE 0xe44
#define DDR_ERR_INT_EN 0xe48
#define DDR_CAPTURE_ATTRIBUTES 0xe4c
#define DDR_CAPTURE_ADDRESS 0xe50
#define DDR_ERR_SBE 0xe58

#ifdef __cplusplus
}
#endif

#endif /* __INCm85xxMemch */