m8560cpmintrctl.h

vxworks MPC8541 BSP

/* m8560CpmIntrCtl.h - Motorola ads 85xx board system-dependent header file */

/* Copyright 1984-2003 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01a,29jul04,mil  Removed BSP header file.
*/

#ifndef __INCm8560CpmIntrCtlh
#define __INCm8560CpmIntrCtlh

#ifdef __cplusplus
    extern "C" {
#endif
#include "m85xxGlobUtil.h"
/* 
 * Maximum number of SCC channels to configure as SIOs. Note that this 
 * assumes sequential usage of SCCs.
 */

#define M85XX_CPM_SICR(base)         (CAST(VUINT16 *)((base) + 0x90c00))
#define M85XX_CPM_SIVEC(base)        (CAST(VUINT8  *)((base) + 0x90c04))
#define M85XX_CPM_SIPNR_H(base)      (CAST(VUINT32 *)((base) + 0x90c08))
#define M85XX_CPM_SIPNR_L(base)      (CAST(VUINT32 *)((base) + 0x90c0c))
#define M85XX_CPM_SCPRR_H(base)      (CAST(VUINT32 *)((base) + 0x90c14))
#define M85XX_CPM_SCPRR_L(base)      (CAST(VUINT32 *)((base) + 0x90c18))
#define M85XX_CPM_SIMR_H(base)       (CAST(VUINT32 *)((base) + 0x90c1c))
#define M85XX_CPM_SIMR_L(base)       (CAST(VUINT32 *)((base) + 0x90c20))
#define M85XX_CPM_SIEXR(base)        (CAST(VUINT32 *)((base) + 0x90c24))
#define M85XX_CPM_SCCR(base)         (CAST(VUINT32 *)((base) + 0x90c80))

/* cpm interrupt numbers  */

#define INUM_CPM_ERROR			0	/* Error */
#define INUM_CPM_I2C			1	/* I2C */
#define INUM_CPM_SPI			2	/* SPI */
#define INUM_CPM_RISC_TIMER		3	/* Risc Timer Table */
#define INUM_CPM_SMC1			4	/* SMC 1 */
#define INUM_CPM_SMC2			5	/* SMC 2 */
#define INUM_CPM_RESERVED6		6	/* reserved */
#define INUM_CPM_RESERVED7		7	/* reserved */
#define INUM_CPM_RESERVED8		8	/* reserved */
#define INUM_CPM_RESERVED9		9	/* reserved */
#define INUM_CPM_RESERVED10		10	/* reserved */
#define INUM_CPM_USB			11	/* USB */
#define INUM_CPM_TIMER1			12	/* Timer 1 */
#define INUM_CPM_TIMER2			13	/* Timer 2 */
#define INUM_CPM_TIMER3			14	/* Timer 3 */
#define INUM_CPM_TIMER4			15	/* Timer 4 */
#define INUM_CPM_RESERVED16		16	/* reserved */
#define INUM_CPM_RESERVED17		17	/* reserved */
#define	INUM_CPM_RESERVED18		18	/* reserved */
#define INUM_CPM_RESERVED19		19	/* reserved */
#define INUM_CPM_RESERVED20		20	/* reserved */
#define INUM_CPM_RESERVED21		21	/* reserved */
#define INUM_CPM_RESERVED22		22	/* reserved */
#define INUM_CPM_RESERVED23		23	/* reserved */
#define INUM_CPM_RESERVED24		24	/* reserved */
#define INUM_CPM_RESERVED25		25	/* reserved */
#define INUM_CPM_RESERVED26		26	/* reserved */
#define INUM_CPM_RESERVED27		27	/* reserved */
#define INUM_CPM_RESERVED28		28	/* reserved */
#define INUM_CPM_RESERVED29		29	/* reserved */
#define INUM_CPM_RESERVED30		30	/* reserved */
#define INUM_CPM_RESERVED31		31	/* reserved */
#define INUM_CPM_FCC1			32	/* FCC1 */
#define INUM_CPM_FCC2			33	/* FCC2 */
#define INUM_CPM_FCC3			34	/* FCC3 */
#define INUM_CPM_RESERVED35		35	/* reserved */
#define INUM_CPM_MCC1			36	/* MCC1 */
#define INUM_CPM_MCC2			37	/* MCC2 */
#define INUM_CPM_RESERVED38		38	/* reserved */
#define INUM_CPM_RESERVED39		39	/* reserved */
#define INUM_CPM_SCC1			40	/* SCC1 */
#define INUM_CPM_SCC2			41	/* SCC2 */
#define INUM_CPM_SCC3			42	/* SCC3 */
#define INUM_CPM_SCC4			43	/* SCC4 */
#define INUM_CPM_TC_LAYER		44	/* TC layer */
#define INUM_CPM_CORE_INTF		45	/* Core interface */
#define INUM_CPM_SDMA_SYS		46	/* SDMA system */
#define INUM_CPM_SDMA_LOC		47	/* SDMA local */
#define INUM_CPM_PC29			48	/* Parallel I/O [29] */
#define INUM_CPM_PC23			49	/* Parallel I/O [23] */
#define INUM_CPM_PC15			50	/* Parallel I/O [15] */
#define INUM_CPM_PC14			51	/* Parallel I/O [14] */
#define INUM_CPM_PC13			52	/* Parallel I/O [13] */
#define INUM_CPM_PC12			53	/* Parallel I/O [12] */
#define INUM_CPM_PC11			54	/* Parallel I/O [11] */
#define INUM_CPM_PC10			55	/* Parallel I/O [10] */
#define INUM_CPM_PC9			56	/* Parallel I/O [9] */
#define INUM_CPM_PC8			57	/* Parallel I/O [8] */
#define INUM_CPM_PC7			58	/* Parallel I/O [7] */
#define INUM_CPM_PC6			59	/* Parallel I/O [6] */
#define INUM_CPM_PC5			60	/* Parallel I/O [5] */
#define INUM_CPM_PC4			61	/* Parallel I/O [4] */
#define INUM_CPM_PC1			52	/* Parallel I/O [1] */
#define INUM_CPM_PC0			63	/* Parallel I/O [0] */

typedef struct m8560VecTbl
    {
    UINT32 intVec;
    void   (*excHandler) ();
    UINT32 param;
    } M8560VEC_TBL;

extern void m85xxCpmIntConnect (int inum, VOIDFUNCPTR handler, int *param);
extern void m85xxCpmIntEnable (int vector);
extern void m85xxCpmIntDisable (int vector);

#ifdef __cplusplus
}
#endif

#endif /* __INCm8560CpmIntrCtlh */