mot85xxpci.c

vxworks MPC8541 BSP

/* mot85xxPci.c - Motorola ads 85xx PCI Bridge functions */

/* Copyright 1984-2004 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01d,28oct04,jln  add PCI2 support
01c,04aug03,dtr  Move LAWAR2 to LAWAR3.
01b,30jul03,dtr  Fixing some magic numbers and setting PCI snoop.
01a,04jul02,dtr  File created.
*/

/* PCI Host Bridge setup File */

#include "vxWorks.h"
#include "config.h"
#include "sysLib.h"

#include "drv/pci/pciConfigLib.h"
#include "drv/pci/pciIntLib.h"
#include "drv/pci/pciAutoConfigLib.h"
#include "sysBusPci.h"
#include "mot85xxPci.h"
#include "m85xxMemc.h"

#define MAX_NUM_VECTORS 4

UINT32 pciRegRead(UINT32 *adrs);
void   pciRegWrite(UINT32 *adrs,UINT32 value);

void pciConfigTest(int pciSys);
#define PCI_REG_READ  pciRegRead
#define PCI_REG_WRITE  pciRegWrite


/*************************************************************************
 * 
 * mot85xxBridgeInit - This function performs all the initialisation 
 * required for the Bridge/Interrupts/PCI Bus to function. It does some
 * low level processor initialisation which might normally be done in 
 * romInit as it is optional to do use this and shows what the core 
 * changes required to bring up the bridge.
 * 
 * RETURNS : NONE
 *
 */
/*lint -save -e572*/
/*lint -save -e550*/
void mot85xxBridgeInit()
    {
      STATUS          result;
      volatile UINT32 valRead;

      /* Initialise LAWBAR/LAWAR for PCI */

      *M85XX_LAWBAR3(CCSBAR) = CPU_PCI_MEM_ADRS >> LAWBAR_ADRS_SHIFT;
      *M85XX_LAWAR3(CCSBAR)  = LAWAR_ENABLE | LAWAR_TGTIF_PCI | LAWAR_SIZE_512MB;

#ifdef INCLUDE_SECONDARY_PCI

      *M85XX_LAWBAR4(CCSBAR) = CPU_PCI_MEM_ADRS2 >> LAWBAR_ADRS_SHIFT;
      *M85XX_LAWAR4(CCSBAR)  = LAWAR_ENABLE | LAWAR_TGTIF_PCI2 | LAWAR_SIZE_512MB;

      valRead =  *M85XX_LAWAR4(CCSBAR);
#else
      valRead =  *M85XX_LAWAR3(CCSBAR);
#endif /* INCLUDE_SECONDARY_PCI */

      WRS_ASM("isync");

      /* Set outbound translation window adresses */

      sysPciConfigEnable (1);
   
      result = sysPciConfigWrite(0,0,0,
				 PCI_CFG_BASE_ADDRESS_0,
				 0x4,
				 PCI_BRIDGE_PIMMR_BASE_ADRS);

      /* for PCI 1 */

      PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REG0(CCSBAR)),
		    (CPU_PCI_MEM_ADRS>>12) & 0xfffff);

      PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_TRANS_ADRS_REG0(CCSBAR)),
		    (PCI_MEM_ADRS>>12) & 0xfffff);

      PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REG1(CCSBAR)),
		    (CPU_PCI_MEMIO_ADRS>>12) & 0xfffff);

      PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_TRANS_ADRS_REG1(CCSBAR)),
		    (PCI_MEMIO_ADRS>>12) & 0xfffff);

      PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REG2(CCSBAR)),
		    (CPU_PCI_IO_ADRS>>12) & 0xfffff);

      PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_TRANS_ADRS_REG2(CCSBAR)),
		    (PCI_IO_ADRS>>12) & 0xfffff);

      PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REG0(CCSBAR)),
		    PCI_WINDOW_ENABLE_BIT | PCI_OUT_ATTR_RTT_MEM | \
                    PCI_OUT_ATTR_WTT_MEM | PCI_MEM_SIZE_MASK);

      PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REG1(CCSBAR)),
		    PCI_WINDOW_ENABLE_BIT |PCI_OUT_ATTR_RTT_MEM | \
                    PCI_OUT_ATTR_WTT_MEM | PCI_MEMIO_SIZE_MASK);

      PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REG2(CCSBAR)),
		    PCI_WINDOW_ENABLE_BIT |PCI_OUT_ATTR_RTT_IO | \
                    PCI_OUT_ATTR_WTT_IO | PCI_IO_SIZE_MASK);

      /* Switch on the inbound windows */

      PCI_REG_WRITE((UINT32*)(PCI_INBOUND_BASE_ADRS_REG1(CCSBAR)),
		    (PCI_MSTR_MEM_BUS>>12) & 0xfffff);

      PCI_REG_WRITE((UINT32*)(PCI_INBOUND_TRANS_ADRS_REG1(CCSBAR)),
		    (LOCAL_MEM_LOCAL_ADRS>>12) & 0xfffff);
			  
      PCI_REG_WRITE((UINT32*)(PCI_INBOUND_ATTR_REG1(CCSBAR)),
		    PCI_WINDOW_ENABLE_BIT | \
		    PCI_IN_ATTR_RTT_LM_READ_SNOOP | \
                    PCI_IN_ATTR_RTT_LM_WRITE_SNOOP | PCI_IN_ATTR_TGI_LM | 
		    PCI_LOCAL_MEM_SIZE_MASK);

      PCI_REG_WRITE((UINT32*)(PCI_INBOUND_ATTR_REG2(CCSBAR)),
		    PCI_IN_ATTR_RTT_LM_READ_SNOOP | \
                    PCI_IN_ATTR_RTT_LM_WRITE_SNOOP | PCI_IN_ATTR_TGI_LM | PCI_LOCAL_MEM_SIZE_MASK);

      PCI_REG_WRITE((UINT32*)(PCI_INBOUND_ATTR_REG3(CCSBAR)),
		    PCI_IN_ATTR_RTT_LM_READ_SNOOP | \
                    PCI_IN_ATTR_RTT_LM_WRITE_SNOOP | PCI_IN_ATTR_TGI_LM | PCI_LOCAL_MEM_SIZE_MASK);


      /* configure the bridge as bus master */

      result = sysPciConfigWrite(0,0,0,
				 COMMAND_REGISTER_OFFSET,
				 COMMAND_REGISTER_WIDTH,
				 PCI_CMD_IO_ENABLE |
				 PCI_CMD_MEM_ENABLE | 
				 PCI_CMD_MASTER_ENABLE);

      WRS_ASM("sync;eieio");

#ifdef INCLUDE_SECONDARY_PCI

      sysPciConfigEnable (2);

      /* for PCI 2 */

      PCI_REG_WRITE((UINT32*)(PCI2_OUTBOUND_BASE_ADRS_REG0(CCSBAR)),
		    (CPU_PCI_MEM_ADRS2>>12) & 0xfffff);

      PCI_REG_WRITE((UINT32*)(PCI2_OUTBOUND_TRANS_ADRS_REG0(CCSBAR)),
		    (PCI_MEM_ADRS2>>12) & 0xfffff);

      PCI_REG_WRITE((UINT32*)(PCI2_OUTBOUND_BASE_ADRS_REG1(CCSBAR)),
		    (CPU_PCI_MEMIO_ADRS2>>12) & 0xfffff);

      PCI_REG_WRITE((UINT32*)(PCI2_OUTBOUND_TRANS_ADRS_REG1(CCSBAR)),
		    (PCI_MEMIO_ADRS2>>12) & 0xfffff);

      PCI_REG_WRITE((UINT32*)(PCI2_OUTBOUND_BASE_ADRS_REG2(CCSBAR)),
		    (CPU_PCI_IO_ADRS2>>12) & 0xfffff);

      PCI_REG_WRITE((UINT32*)(PCI2_OUTBOUND_TRANS_ADRS_REG2(CCSBAR)),
		    (PCI_IO_ADRS2>>12) & 0xfffff);

      PCI_REG_WRITE((UINT32*)(PCI2_OUTBOUND_ATTR_REG0(CCSBAR)),
		    PCI_WINDOW_ENABLE_BIT | PCI_OUT_ATTR_RTT_MEM | \
                    PCI_OUT_ATTR_WTT_MEM | PCI_MEM_SIZE_MASK);

      PCI_REG_WRITE((UINT32*)(PCI2_OUTBOUND_ATTR_REG1(CCSBAR)),
		    PCI_WINDOW_ENABLE_BIT |PCI_OUT_ATTR_RTT_MEM | \
                    PCI_OUT_ATTR_WTT_MEM | PCI_MEMIO_SIZE_MASK);

      PCI_REG_WRITE((UINT32*)(PCI2_OUTBOUND_ATTR_REG2(CCSBAR)),
		    PCI_WINDOW_ENABLE_BIT |PCI_OUT_ATTR_RTT_IO | \
                    PCI_OUT_ATTR_WTT_IO | PCI_IO_SIZE_MASK);

      /* Switch on the inbound windows */

      PCI_REG_WRITE((UINT32*)(PCI2_INBOUND_BASE_ADRS_REG1(CCSBAR)),
		    (PCI_MSTR_MEM_BUS>>12) & 0xfffff);

      PCI_REG_WRITE((UINT32*)(PCI2_INBOUND_TRANS_ADRS_REG1(CCSBAR)),
		    (LOCAL_MEM_LOCAL_ADRS>>12) & 0xfffff);
			  
      PCI_REG_WRITE((UINT32*)(PCI2_INBOUND_ATTR_REG1(CCSBAR)),
		    PCI_WINDOW_ENABLE_BIT | \
		    PCI_IN_ATTR_RTT_LM_READ_SNOOP | \
                    PCI_IN_ATTR_RTT_LM_WRITE_SNOOP | PCI_IN_ATTR_TGI_LM | 
		    PCI_LOCAL_MEM_SIZE_MASK);

      PCI_REG_WRITE((UINT32*)(PCI2_INBOUND_ATTR_REG2(CCSBAR)),
		    PCI_IN_ATTR_RTT_LM_READ_SNOOP | \
                    PCI_IN_ATTR_RTT_LM_WRITE_SNOOP | PCI_IN_ATTR_TGI_LM | PCI_LOCAL_MEM_SIZE_MASK);

      PCI_REG_WRITE((UINT32*)(PCI2_INBOUND_ATTR_REG3(CCSBAR)),
		    PCI_IN_ATTR_RTT_LM_READ_SNOOP | \
                    PCI_IN_ATTR_RTT_LM_WRITE_SNOOP | PCI_IN_ATTR_TGI_LM | PCI_LOCAL_MEM_SIZE_MASK);

      result = sysPciConfigWrite(0,0,0,
				 COMMAND_REGISTER_OFFSET,
				 COMMAND_REGISTER_WIDTH,
				 PCI_CMD_IO_ENABLE |
				 PCI_CMD_MEM_ENABLE | 
				 PCI_CMD_MASTER_ENABLE);

      WRS_ASM("sync;eieio");

      /* change to default PCI system 1 */

      sysPciConfigEnable (1);

#endif /* INCLUDE_SECONDARY_PCI */
    }
/*lint -restore*/
/*lint -restore*/

/********************************************************
 * pciRegWrite - write to memeory-map PCI registers
 *
 * This function write ATMU registers for PCI
 * 
 * RETURN: N/A
 */
 
void pciRegWrite(UINT32 *adrs,UINT32 value)
    {
    *adrs = value;
    WRS_ASM("sync;eieio");
    }

/********************************************************
 * pciRegRead - read from memeory-map PCI registers
 *
 * This function read ATMU registers for PCI
 * 
 * RETURN: N/A
 */

UINT32 pciRegRead(UINT32 *adrs)
    {
    return (*adrs);
    }

/********************************************************
 * pciConfigTest - dump on-chip PCI configuration header
 *
 * This function print out PCI configuration header
 * 
 * RETURN: N/A
 */

void pciConfigTest
    (
    int pciSys
    )
    {
    int loop;
    UINT32 var;

    if (pciSys == 1)
        sysPciConfigEnable (1);
    else
        sysPciConfigEnable (2);

    for(loop = 0; loop < 0x40; loop += 4)
        {
        sysPciConfigRead(0,0,0,loop,0x4,&var);
        printf("Word %d Value %x\n",loop,var);
        }
    }