sysmotfcc2end.c

vxworks MPC8541 BSP

* sysMiiPhyInit - initialize and configure the PHY devices
*
* This routine scans, initializes and configures the PHY device.
*
* RETURNS: OK, or ERROR.
*/

LOCAL STATUS sysMiiPhyInit
    (
    PHY_INFO * pPhyInfo
    )
    {
    int    retVal,retValNull;
    VUINT16 miiSpecial;

    retVal = miiPhyInit (pPhyInfo);

    /* Set reg 16 of MII to proper default */
    miiSpecial = 0x0400; /* Base-TX */
    MII_WRITE(pPhyInfo->phyAddr,16,miiSpecial,retValNull);

    return retVal;
    }
/*ling +e550*/
/***********************************************************************
*
* sysFccEnetEnable - enable the MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to enable the Ethernet device and to connect the MII interface to the FCC.
*
* RETURNS: OK, or ERROR if the FCC controller cannot be enabled.
*/

STATUS sysFccEnetEnable
    (
    UINT32  immrVal,    /* base address of the on-chip RAM */
    UINT8   fccNum  /* FCC being used */
    )
    {
    int             intLevel;

    intLevel = intLock ();

    /* set Port A and C to use MII signals */

    if (fccNum == 1)
        {
        *M8260_IOP_PCPAR(immrVal) |=  (PC21 | PC20);
        *M8260_IOP_PCPAR(immrVal) &= ~(PC14 | PC13);
        *M8260_IOP_PCSO(immrVal)  &= ~(PC21 | PC20);
        *M8260_IOP_PCDIR(immrVal) &= ~(PC21 | PC20);

        *M8260_IOP_PAPAR(immrVal) |=  (PA31 | PA30 | PA29 | PA28 | PA27 | 
                                       PA26 | PA21 | PA20 | PA19 | PA18 | 
                                       PA17 | PA16 | PA15 | PA14);

        *M8260_IOP_PADIR(immrVal) |=  (PA29 | PA28 | PA21 | PA20 | PA19 | 
                                       PA18);
        *M8260_IOP_PADIR(immrVal) &= ~(PA31 | PA30 | PA27 | PA26 | PA17 | 
                                       PA16 | PA15 | PA14);

        *M8260_IOP_PASO(immrVal)  &= ~(PA21 | PA20 | PA19 | PA18 | PA17 | 
                                       PA16 | PA15 | PA14);
        *M8260_IOP_PASO(immrVal)  |=  (PA31 | PA30 | PA29 | PA28 | PA27 | 
                                       PA26);

        /* connect FCC1 clocks */

        *M8260_CMXFCR (immrVal) |= (M8260_CMXFCR_R1CS_CLK12 | 
                                    M8260_CMXFCR_T1CS_CLK11);

        /* NMSI mode */

        *M8260_CMXFCR (immrVal) &= ~(M8260_CMXFCR_FC1_MUX);
        }

    /* set Port B and C to use MII signals */

    if (fccNum == 2)
        {
        *M8260_IOP_PCPAR(immrVal) |=  (PC19 | PC18);
        *M8260_IOP_PCPAR(immrVal) &= ~(PC14 | PC13);
        *M8260_IOP_PCSO(immrVal)  &= ~(PC19 | PC18);
        *M8260_IOP_PCDIR(immrVal) &= ~(PC19 | PC18);

        *M8260_IOP_PBPAR(immrVal) |=  (PB31 | PB30 | PB29 | PB28 | PB27 | 
                                       PB26 | PB25 | PB24 | PB23 | PB22 | 
                                       PB21 | PB20 | PB19 | PB18);

        *M8260_IOP_PBDIR(immrVal) |=  (PB31 | PB29 | PB25 | PB24 | PB23 | 
                                       PB22);
        *M8260_IOP_PBDIR(immrVal) &= ~(PB30 | PB28 | PB27 | PB26 | PB21 | 
                                       PB20 | PB19 | PB18);

        *M8260_IOP_PBSO(immrVal)  &= ~(PB31 | PB30 | PB28 | PB27 | PB26 | 
                                       PB25 | PB24 | PB23 | PB22 | PB21 | 
                                       PB20 | PB19 | PB18);
        *M8260_IOP_PBSO(immrVal)  |=  (PB29);

        /* connect FCC2 clocks */

        *M8260_CMXFCR (immrVal) |= (M8260_CMXFCR_R2CS_CLK14 | 
                                    M8260_CMXFCR_T2CS_CLK13);

        /* NMSI mode */

        *M8260_CMXFCR (immrVal) &= ~(M8260_CMXFCR_FC2_MUX);
        }

        /* set Port B and C to use MII signals */

    if (fccNum == 3)
        {
#if 0
        *M8260_IOP_PCPAR(immrVal) |=  (PC17 | PC16);
        *M8260_IOP_PCPAR(immrVal) &= ~(PC14 | PC13);
        *M8260_IOP_PCSO(immrVal)  &= ~(PC17 | PC16);
        *M8260_IOP_PCDIR(immrVal) &= ~(PC17 | PC16);

        *M8260_IOP_PBPAR(immrVal) |=  (PB17 | PB16 | PB15 | PB14 | PB13 |
                                       PB12 | PB11 | PB10 | PB9  | PB8  |
                                       PB7  | PB6  | PB5  | PB4);

        *M8260_IOP_PBDIR(immrVal) |=  (PB15 | PB14 | PB7  | PB6  | PB5  |
                                       PB4);
        *M8260_IOP_PBDIR(immrVal) &= ~(PB17 | PB16 | PB13 | PB12 | PB11 |
                                       PB10 | PB9  | PB8);

        *M8260_IOP_PBSO(immrVal)  &= ~(PB17 | PB16 | PB15 | PB14 | PB13 |
                                       PB12 | PB11 | PB10 | PB9  | PB8  |
                                       PB7  | PB6  | PB5  | PB4);
#else
        *M8260_IOP_PDSO(immrVal)  |=  (PD4);
        *M8260_IOP_PCSO(immrVal)  &= ~(PC17 | PC16);
        *M8260_IOP_PBDIR(immrVal) |=  (PB15 | PB14 | PB7  | PB6  | PB5  | PB4);
        *M8260_IOP_PCDIR(immrVal) |=  (PC27);
        *M8260_IOP_PDDIR(immrVal) |=  (PD4);
        *M8260_IOP_PCPAR(immrVal) |=  (PC16 | PC17);
        *M8260_IOP_PCPAR(immrVal) &= ~(PC14 | PC13);
        *M8260_IOP_PCPAR(immrVal) |=  (PC3  | PC2  | PC27);
        *M8260_IOP_PBPAR(immrVal) |=  (PB17 | PB16 | PB15 | PB14 | PB13 | 
                                       PB12 | PB11 | PB10 | PB9  | PB8  | 
                                       PB7  | PB6  | PB5  | PB4);
        *M8260_IOP_PDPAR(immrVal) |=  (PD4);
#endif

        /* connect FCC3 clocks */

        *M8260_CMXFCR (immrVal) |= (M8260_CMXFCR_R3CS_CLK15 | 
                                    M8260_CMXFCR_T3CS_CLK16);

        /* NMSI mode */

        *M8260_CMXFCR (immrVal) &= ~(M8260_CMXFCR_FC3_MUX);
        }

    intUnlock (intLevel);

    taskDelay (sysClkRateGet() >> 2);

    return(OK);
    }

/***********************************************************************
*
* sysFccEnetDisable - disable MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to disable the Ethernet device and the MII interface to the FCC
* controller.  This involves restoring the default values for all the Port
* B and C signals.
*
* RETURNS: OK, always.
*/

STATUS sysFccEnetDisable
    (
    UINT32  immrVal,    /* base address of the on-chip RAM */
    UINT8   fccNum  /* FCC being used */
    )
    {
    int             intLevel;

    intLevel = intLock ();

    /*
     * configure all Port B and C pins previously used as general
     * purpose input pins
     */

    if (fccNum == 1)
        {
        *M8260_IOP_PCPAR(immrVal) &= ~(PC21 | PC20);

        *M8260_IOP_PCDIR(immrVal) &= ~(PC13);

        *M8260_IOP_PAPAR(immrVal) &= ~(PA31 | PA30 | PA29 | PA28 | PA27 | 
                                       PA26 | PA21 | PA20 | PA19 | PA18 | 
                                       PA17 | PA16 | PA15 | PA14);

        *M8260_IOP_PADIR(immrVal) &= ~(PA29 | PA28 | PA21 | PA20 | PA19 | 
                                       PA18);

        /* Disable the interrupt */

        m85xxCpmIntDisable (INUM_CPM_FCC1);
        }

    if (fccNum == 2)
        {
        *M8260_IOP_PCPAR(immrVal) &= ~(PC19 | PC18);

        *M8260_IOP_PCDIR(immrVal) &= ~(PC13);

        *M8260_IOP_PBPAR(immrVal) &= ~(PB31 | PB30 | PB29 | PB28 | PB27 | 
                                       PB26 | PB25 | PB24 | PB23 | PB22 | 
                                       PB21 | PB20 | PB19 | PB18);

        *M8260_IOP_PBDIR(immrVal) &= ~(PB31 | PB29 | PB25 | PB24 | PB23 | 
                                       PB22);

        /* Disable the interrupt */

        m85xxCpmIntDisable (INUM_CPM_FCC2);
        }

    if (fccNum == 3)
        {
        *M8260_IOP_PCPAR(immrVal) &= ~(PC17 | PC16);

        *M8260_IOP_PCDIR(immrVal) &= ~(PC13);

        *M8260_IOP_PBPAR(immrVal) &= ~(PB17 | PB16 | PB15 | PB14 | PB13 | 
                                       PB12 | PB11 | PB10 | PB9  | PB8  | 
                                       PB7  | PB6  | PB5  | PB4);

        *M8260_IOP_PBDIR(immrVal) &= ~(PB15 | PB14 | PB7  | PB6  | PB5  | 
                                       PB4);

        /* Disable the interrupt */

        m85xxCpmIntDisable (INUM_CPM_FCC3);
        }

    intUnlock (intLevel);

    return(OK);
    }


/***********************************************************************
*
* sysFccEnetCommand - issue a command to the Ethernet interface controller
*
* RETURNS: OK, or ERROR if the Ethernet controller could not be restarted.
*/

STATUS sysFccEnetCommand
    (
    UINT32      immrVal,        /* base address of the on-chip RAM */
    UINT8   fccNum,     /* FCC being used */
    UINT16  command
    )
    {
    return (OK);
    }

#ifndef NSDELAY
#define MOTOROLA_FCC_LOOP_NS 2

#define NSDELAY(nsec)                                                   \
    {                                                                   \
    volatile int nx = 0;                                                \
    volatile int loop = (int)(nsec*MOTOROLA_FCC_LOOP_NS);               \
                                                                        \
    for (nx = 0; nx < loop; nx++)                                       \
        ;                                                               \
    }
#endif /* NSDELAY */

/***********************************************************************
*
* sysFccMiiBitWr - write one bit to the MII interface
*
* This routine writes the value in <bitVal> to the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
* If <bitVal> is NONE, then the MDIO pin should be left in high-impedance
* state.
*
* SEE ALSO: sysFccMiiBitRd()
*
* RETURNS: OK, or ERROR.
*/
STATUS sysFccMiiBitWr
    (
    UINT32      immrVal,        /* base address of the on-chip RAM */
    UINT8   fccNum,     /* FCC being used */
    INT32        bitVal          /* the bit being written */
    )
    {
    miiBitWrCount++;
    /*
     * we create the timing reference for transfer of info on the MDIO line
     * MDIO is mapped on PC14, MDC on PC13. We need to keep the same data
     * on MDIO for at least 400 nsec.
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(PC14 | PC13);
    *M8260_IOP_PCDIR(immrVal) |= (PC14 | PC13);
    *M8260_IOP_PCDAT(immrVal) |= (PC13);

    switch (bitVal)
    {
    case 0:
        *M8260_IOP_PCDAT(immrVal) &= ~(PC14);
        break;
    case 1:
        *M8260_IOP_PCDAT(immrVal) |= (PC14);
        break;
    case ((INT32) NONE):
        /* put it in high-impedance state */
        *M8260_IOP_PCDIR(immrVal) &= ~(PC14);
        break;
    default:
        return (ERROR);
    }

    /* delay about 200 nsec. */

    NSDELAY (200);

    /* now we toggle the clock and delay again */

    *M8260_IOP_PCDAT(immrVal) &= ~(PC13);

    NSDELAY (200);

    return (OK);
    }

/***********************************************************************
*
* sysFccMiiBitRd - read one bit from the MII interface
*
* This routine reads one bit from the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
*
* SEE ALSO: sysFccMiiBitWr()
*
* RETURNS: OK, or ERROR.
*/

STATUS sysFccMiiBitRd
    (
    UINT32      immrVal,        /* base address of the on-chip RAM */
    UINT8   fccNum,     /* FCC being used */
    INT8 *      bitVal          /* the bit being read */
    )
    {
    miiBitRdCount++;
    /*
     * we create the timing reference for transfer of info on the MDIO line
     * MDIO is mapped on PC14, MDC on PC13. We can read data on MDIO after
     * at least 400 nsec.
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(PC14 | PC13);
    *M8260_IOP_PCDIR(immrVal) &= ~(PC14);

    *M8260_IOP_PCDIR(immrVal) |= (PC13);
    *M8260_IOP_PCDAT(immrVal) |= (PC13);

    /* delay about 200 nsec. */

    NSDELAY (200);

    /* now we toggle the clock and delay again */

    *M8260_IOP_PCDAT(immrVal) &= ~(PC13);

    NSDELAY (200);

    /* we can now read the MDIO data on PC14 */

    *bitVal = (*M8260_IOP_PCDAT(immrVal) & (PC14)) >> 17;

    return (OK);
    }

#endif /* INCLUDE_MOT_FCC_END */

UINT32 m8260InumToIvec(UINT32 val)
{
return val;
}