📄 configboard.h
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#ifdef INCLUDE_FLASH_MEM1# define FLASH1_MEM_ADRS LBC_CS1_ADRS /* base address of flash */# define FLASH1_MEM_SIZE LBC_CS1_SIZE /* 64 Mbytes total flash size */#endif /* INCLUDE_FLASH_MEM1 */#define INCLUDE_FLASH_MEM2#ifdef INCLUDE_FLASH_MEM2# define FLASH2_MEM_ADRS LBC_CS2_ADRS /* base address of flash */# define FLASH2_MEM_SIZE LBC_CS2_SIZE /* 64 Mbytes total flash size */#endif /* INCLUDE_FLASH_MEM2 *//* * NVRAM configuration * This NVRAM is implemented via the Flash Memory. *//*目前flash最后0x1000空间用来保存各种参数，保留的0x600为nvarm和bddata两个区域扩充的*/ #define FLASH_PARA_SIZE 0x1000#define RESV_PARA_SIZE 0x600#define NV_RAM_SIZE 0x400#define BD_DATA_SIZE 0x400#define VER_PARA_SIZE 0x200#define NV_OFF_BOOT0 0x0000 /* Boot string 0 (256b) */#define NV_OFF_BOOT1 0x0100 /* Boot string 1 (256b) */#define NV_OFF_BOOT2 0x0200 /* Boot string 2 (256b)*/#define NV_OFF_ACTIVEBOOT 0x0300 /* Active boot string, 0 to 2 (1b) */#define NV_OFF_NETWORKBOOT 0x0301 /* Network boot string, 0 to 2 (1b) */#define NV_OFF_UNUSED1 0x0302 /* Unused (2b) */#define NV_OFF_IMAGEADDR 0x0304 /* vxWorks image address (4b) */#define NV_OFF_IMAGESIZE 0x0308 /* vxWorks image size (4b) */#define NV_OFF_UNUSED2 0x030C /* Unused (4b) */#define NV_OFF_MACADDR1 0x0310 /* MAC address (6b) */#define NV_OFF_UNUSED3 0x0316 /* Unused (2b) */#define NV_OFF_MACADDR2 0x0318 /* MAC address (6b) */#define NV_OFF_UNUSED4 0x031E /* Unused (2b) */#define NV_OFF_MACADDR3 0x0320 /* MAC address (6b) */#define NV_OFF_UNUSED5 0x0326 /* Unused (2b) */#define NV_OFF_FREE 0x0328#define FLASH_PROTECT_PORT PC8/* Board Control and Status Register definitions */#define BCSR_BASE_ADRS LBC_CS4_ADRS /* Base address */#define BCSR_SIZE LBC_CS4_SIZE /* 1M of address space */#define BCSR_REG(off) (*(volatile UINT8 *)(BCSR_BASE_ADRS + (off)))#define SYS_BRDID_GET() (~BCSR_REG(0))#define SYS_WD_ENABLE() (BCSR_REG(0x44) |= 0x1)#define SYS_WD_DISABLE() (BCSR_REG(0x44) &= ~0x1)#define SYS_WD_RESET() (BCSR_REG(0x40) ^= 0x1)#ifdef LED_MEM_MAPPED# define RED_ON ((BCSR_REG(0xd0) & ~0x1) | 0x2)# define GRE_ON ((BCSR_REG(0xd0) & ~0x2) | 0x1)# define YEL_ON ((BCSR_REG(0xd0) | 0x3))# define ALL_OFF ((BCSR_REG(0xd0) & ~0x3))# define SYS_LED_RUN(val) ((BCSR_REG(0xd0) = val))#else# define SYS_LED_ADDR (CCSBAR + 0x090D50)# define RED_ON ((*(volatile UINT32 *)SYS_LED_ADDR | PC9) & ~PC10)# define GRE_ON ((*(volatile UINT32 *)SYS_LED_ADDR | PC10) & ~PC9)# define YEL_ON ((*(volatile UINT32 *)SYS_LED_ADDR & ~(PC9 | PC10)))# define ALL_OFF ((*(volatile UINT32 *)SYS_LED_ADDR | (PC9 | PC10)))# define SYS_LED_RUN(val) { \ *(volatile UINT32 *)(CCSBAR + 0x090D40) |= (PC9 | PC10); \ *(volatile UINT32 *)SYS_LED_ADDR = val; \ }#endif /* LED_MEM_MAPPED */#define N_SIO_CHANNELS 2 /* No. serial I/O channels *//* SPI definitions */#ifdef INCLUDE_MOT_SPI#define SPI_PRAM_ADDR_OFFSET (DPRAM_BANK_ADDR5 + 0x400)#define SPI_RXBD_ADDR_OFFSET (SPI_PRAM_ADDR_OFFSET + 0x40)#define SPI_TXBD_ADDR_OFFSET (SPI_RXBD_ADDR_OFFSET + 0x8)#define SPI_RBUF_ADDR_OFFSET (SPI_TXBD_ADDR_OFFSET + 0x8)#define SPI_TBUF_ADDR_OFFSET (SPI_RBUF_ADDR_OFFSET + 0x8)#endif /* INCLUDE_MOT_SPI *//* I2C definitions */#ifdef INCLUDE_MOT_I2C#define I2C_PRAM_ADDR_OFFSET (DPRAM_BANK_ADDR5 + 0x500)#define I2C_RXBD_ADDR_OFFSET (I2C_PRAM_ADDR_OFFSET + 0x40)#define I2C_TXBD_ADDR_OFFSET (I2C_RXBD_ADDR_OFFSET + 0x8)#define I2C_RBUF_ADDR_OFFSET (I2C_TXBD_ADDR_OFFSET + 0x8)#define I2C_TBUF_ADDR_OFFSET (I2C_RBUF_ADDR_OFFSET + 0x8)#endif /* INCLUDE_MOT_I2C *//* CPU type in the PVR */#define CPU_TYPE_8260 0xAAAA /* value for PPC8260 */#define CPU_TYPE_8266 0xBBBB /* value for PPC8266 */#define CPU_REV_A1_MASK_NUM 0x0010 /* revision mask num */#define HIP4_ID 0x80810000 /* device ID via PVR */#define HIP4_MASK 0xFFFF0000 /* mask upper word *//* This value is the setting for the MPTPR[PTP] Refresh timer prescaler. * The value is dependent on the OSCILLATOR_FREQ value. For other values * a conditionally compiled term must be created here for that OSCILLATOR_FREQ * value. * * BRGCLK_DIV_FACTOR * Baud Rate Generator division factor - 0 for division by 4 * 1 for division by 16 * 2 for division by 64 * 3 for division by 256 */#define DIV_FACT_4 0#define DIV_FACT_16 1#define DIV_FACT_64 2#define DIV_FACT_256 3#if (OSCILLATOR_FREQ == FREQ_66_MHZ)# define TPR 0x2000# define BRGCLK_DIV_FACTOR DIV_FACT_16#endif#define M8260_BRGC_DIVISOR BRGCLK_DIV_FACTOR#define _PPC_BUCSR_FI 0x200 /* Invalidate branch cache */#define _PPC_BUCSR_E 0x1 /* Enable branch prediction *//* Define Clock Speed and Source */#define FREQ_33_MHZ 33333333#define FREQ_50_MHZ 49999999#define FREQ_66_MHZ 66666666#define FREQ_100_MHZ 99999999#define FREQ_133_MHZ 133333333#define FREQ_150_MHZ 149999999#define FREQ_166_MHZ 166666666#define FREQ_200_MHZ 199999999#define FREQ_233_MHZ 233333333#define FREQ_266_MHZ 266666666#define FREQ_300_MHZ 299999999#define FREQ_450_MHZ 449999999#define FREQ_800_MHZ 799999999/* Port A, B, C and D Defines */#define PA31 (0x00000001)#define PA30 (0x00000002)#define PA29 (0x00000004)#define PA28 (0x00000008)#define PA27 (0x00000010)#define PA26 (0x00000020)#define PA25 (0x00000040)#define PA24 (0x00000080)#define PA23 (0x00000100)#define PA22 (0x00000200)#define PA21 (0x00000400)#define PA20 (0x00000800)#define PA19 (0x00001000)#define PA18 (0x00002000)#define PA17 (0x00004000)#define PA16 (0x00008000)#define PA15 (0x00010000)#define PA14 (0x00020000)#define PA13 (0x00040000)#define PA12 (0x00080000)#define PA11 (0x00100000)#define PA10 (0x00200000)#define PA9 (0x00400000)#define PA8 (0x00800000)#define PA7 (0x01000000)#define PA6 (0x02000000)#define PA5 (0x04000000)#define PA4 (0x08000000)#define PA3 (0x10000000)#define PA2 (0x20000000)#define PA1 (0x40000000)#define PA0 (0x80000000)#define PB31 (0x00000001)#define PB30 (0x00000002)#define PB29 (0x00000004)#define PB28 (0x00000008)#define PB27 (0x00000010)#define PB26 (0x00000020)#define PB25 (0x00000040)#define PB24 (0x00000080)#define PB23 (0x00000100)#define PB22 (0x00000200)#define PB21 (0x00000400)#define PB20 (0x00000800)#define PB19 (0x00001000)#define PB18 (0x00002000)#define PB17 (0x00004000)#define PB16 (0x00008000)#define PB15 (0x00010000)#define PB14 (0x00020000)#define PB13 (0x00040000)#define PB12 (0x00080000)#define PB11 (0x00100000)#define PB10 (0x00200000)#define PB9 (0x00400000)#define PB8 (0x00800000)#define PB7 (0x01000000)#define PB6 (0x02000000)#define PB5 (0x04000000)#define PB4 (0x08000000)#define PC31 (0x00000001)#define PC30 (0x00000002)#define PC29 (0x00000004)#define PC28 (0x00000008)#define PC27 (0x00000010)#define PC26 (0x00000020)#define PC25 (0x00000040)#define PC24 (0x00000080)#define PC23 (0x00000100)#define PC22 (0x00000200)#define PC21 (0x00000400)#define PC20 (0x00000800)#define PC19 (0x00001000)#define PC18 (0x00002000)#define PC17 (0x00004000)#define PC16 (0x00008000)#define PC15 (0x00010000)#define PC14 (0x00020000)#define PC13 (0x00040000)#define PC12 (0x00080000)#define PC11 (0x00100000)#define PC10 (0x00200000)#define PC9 (0x00400000)#define PC8 (0x00800000)#define PC7 (0x01000000)#define PC6 (0x02000000)#define PC5 (0x04000000)#define PC4 (0x08000000)#define PC3 (0x10000000)#define PC2 (0x20000000)#define PC1 (0x40000000)#define PC0 (0x80000000)#define PD31 (0x00000001)#define PD30 (0x00000002)#define PD29 (0x00000004)#define PD28 (0x00000008)#define PD27 (0x00000010)#define PD26 (0x00000020)#define PD25 (0x00000040)#define PD24 (0x00000080)#define PD23 (0x00000100)#define PD22 (0x00000200)#define PD21 (0x00000400)#define PD20 (0x00000800)#define PD19 (0x00001000)#define PD18 (0x00002000)#define PD17 (0x00004000)#define PD16 (0x00008000)#define PD15 (0x00010000)#define PD14 (0x00020000)#define PD13 (0x00040000)#define PD12 (0x00080000)#define PD11 (0x00100000)#define PD10 (0x00200000)#define PD9 (0x00400000)#define PD8 (0x00800000)#define PD7 (0x01000000)#define PD6 (0x02000000)#define PD5 (0x04000000)#define PD4 (0x08000000)#ifdef __cplusplus }#endif /* __cplusplus */#endif /* INCconfigBoardh */⌨️ 快捷键说明
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