configboard.h

vxworks MPC8541 BSP

/* configBoard.h - Motorola MPC85xx ADS board header */

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01t,28jul04,dtr  Mod for PCI DEVNO with RevA board.
01s,31mar04,dtr  Add a new PCI ID for rev2 silicon.
01r,12feb04,dtr  Add in extra DDR register defines.
01q,04feb04,dtr  Adding in DDRDLL reg define.
01p,08oct03,dtr  Adding in DLL debug registers.
01o,08sep03,dtr  Fixing windows compilation.
01n,22aug03,dtr  Adding General registers.
01m,04aug03,dtr  Changing allocation of LAWBAR/LAWAR registers to accomdate
                 LBC SDRAM.
01l,07jul03,mil  Added offsets for SCC regs.
01k,08jul02,dtr  Adding some PCI defines and macros.
*/

/*
This file contains I/O addresses and related constants for the
Motorola MPC85xx ADS board. 
*/

#ifndef	INCconfigBoardh
#define	INCconfigBoardh

#ifdef __cplusplus
    extern "C" {
#endif /* __cplusplus */

#define BUS	0				/* bus-less board */
#define CPU	PPC85XX			/* CPU type */

/*
 * This define must be set to the value of the resonant oscillator.
 * For the rev1.8 board default switch settings are for 33MHz
 */

#define	OSCILLATOR_FREQ		FREQ_66_MHZ
#define CORE_FREQUENCY		FREQ_800_MHZ
#define CPM_FREQUENCY		FREQ_266_MHZ
#define BUS_FREQUENCY		FREQ_66_MHZ
#define PCI_FREQUENCY		FREQ_66_MHZ
#define DEC_CLOCK_FREQ		OSCILLATOR_FREQ

/* clock rates */

#define	SYS_CLK_RATE_MIN	1		/* minimum system clock rate */
#define	SYS_CLK_RATE_MAX	8000	/* maximum system clock rate */
#define	AUX_CLK_RATE_MIN	1		/* minimum auxiliary clock rate */
#define	AUX_CLK_RATE_MAX	8000	/* maximum auxiliary clock rate */
#define WDT_RATE_MIN		(sysTimerClkFreq / (1 << 29))
#define WDT_RATE_MAX		(sysTimerClkFreq / (1 << 21))

/* Base Address of Memory Mapped Registers */

#define CCSBAR						0xfe000000

#define FLASH0_MAP_ADRS				0xff000000		/* tlb mapped to 4GB - 16MB */

#define INCLUDE_LOCAL_MEM2

#ifdef  INCLUDE_LOCAL_MEM2
#   define LOCAL_MEM_LOCAL_ADRS2	0x20000000		/* Base of RAM */
#   define LOCAL_MEM_SIZE2			0x04000000		/* 64 Mbyte memory available */
#endif  /* INCLUDE_LOCAL_MEM2 */

#define INCLUDE_DDR_SDRAM

#ifdef  INCLUDE_DDR_SDRAM
#   define DDR_SDRAM_LOCAL_ADRS		LOCAL_MEM_LOCAL_ADRS
#   define DDR_SDRAM_LOCAL_SIZE		LOCAL_MEM_SIZE
#endif  /* INCLUDE_DDR_SDRAM */

#undef  INCLUDE_LBC_SDRAM

#ifdef  INCLUDE_LBC_SDRAM
#   define LBC_SDRAM_LOCAL_ADRS		LOCAL_MEM_LOCAL_ADRS2
#   define LBC_SDRAM_LOCAL_SIZE		LOCAL_MEM_SIZE2
#endif  /* INCLUDE_LBC_SDRAM */

#define L2SRAM_ADDR					0x7ffc0000
#define L2SRAM_WINDOW_SIZE			0x40000

#define DPRAM_BANK_ADDR1			0x0000
#define DPRAM_BANK_ADDR2			0x0800
#define DPRAM_BANK_ADDR3			0x1000
#define DPRAM_BANK_ADDR4			0x1800
#define DPRAM_BANK_ADDR5			0x8000
#define DPRAM_BANK_ADDR6			0x8800
#define DPRAM_BANK_ADDR7			0x9000
#define DPRAM_BANK_ADDR8			0x9800

/* PCI support */

#ifdef  INCLUDE_PCI

/* PCI based addresses */

#define PCI_MEM_ADRS				0x80000000
#define PCI_MEM_SIZE				0x04000000
#define PCI_MEMIO_ADRS				0x90000000
#define PCI_MEMIO_SIZE				0x04000000
#define PCI_IO_ADRS					0xa0000000
#define PCI_IO_SIZE					0x04000000

#define PCI_MEM_SIZE_MASK			PCI_ATTR_WS_64M
#define PCI_MEMIO_SIZE_MASK			PCI_ATTR_WS_64M
#define PCI_IO_SIZE_MASK			PCI_ATTR_WS_64M

/* CPU based addresses */

#define CPU_PCI_MEM_ADRS			0x80000000
#define CPU_PCI_MEM_SIZE			PCI_MEM_SIZE
#define CPU_PCI_MEMIO_ADRS			0x90000000
#define CPU_PCI_MEMIO_SIZE			PCI_MEMIO_SIZE
#define CPU_PCI_IO_ADRS				0xa0000000
#define CPU_PCI_IO_SIZE				PCI_IO_SIZE

/* CPU from PCI bus */

#define PCI_MSTR_MEM_BUS			0x00000000
#define PCI_MSTR_MEM_SIZE			0x40000000
#define PCI_BRIDGE_PIMMR_BASE_ADRS	0x40000000

/* CPU Address that is visible from PCI */

#define PCI_LOCAL_MEM_BUS			0x00000000
#define PCI_LOCAL_MEM_SIZE			PCI_MSTR_MEM_SIZE
#define PCI_LOCAL_MEM_SIZE_MASK		PCI_ATTR_WS_1G

#ifdef  INCLUDE_SECONDARY_PCI

#define PCI_MEM_ADRS2				0xb0000000
#define PCI_MEMIO_ADRS2				0xc0000000
#define PCI_IO_ADRS2				0xd0000000

#define CPU_PCI_MEM_ADRS2			PCI_MEM_ADRS2
#define CPU_PCI_MEMIO_ADRS2			PCI_MEMIO_ADRS2
#define CPU_PCI_IO_ADRS2			PCI_IO_ADRS2

#endif  /* INCLUDE_SECONDARY_PCI */

/* PCI (non-prefetchable) memory adrs to CPU (60x bus) adrs */

#define PCI_MEMIO2LOCAL(x) \
        (((UINT32)x - PCI_MEMIO_ADRS) + CPU_PCI_MEMIO_ADRS)

/* PCI IO memory adrs to CPU (60x bus) adrs */

#define PCI_IO2LOCAL(x) \
        (((UINT32)x - PCI_IO_ADRS) + CPU_PCI_IO_ADRS)

/* PCI memory adrs to CPU (60x bus) adrs */

#define PCI_MEM2LOCAL(x) \
        (((UINT32)x - PCI_MEM_ADRS) + CPU_PCI_MEM_ADRS)

/* 60x bus adrs to PCI (non-prefetchable) memory adrs */

#define LOCAL2PCI_MEMIO(x) \
        ((int)(x) + PCI_MSTR_MEM_BUS)

#define PCI_AUTO_CONFIG_ADRS	0x4c00

#define NUM_PCI_SLOTS			0x4			/* 4 PCI slots: 0 to 3 */

#define PCI_XINT1_LVL			0x0			/* PCI XINT1 routed to IRQ0 */
#define PCI_XINT2_LVL			0x1			/* PCI XINT2 routed to IRQ1 */
#define PCI_XINT3_LVL			0x2			/* PCI XINT3 routed to IRQ2 */
#define PCI_XINT4_LVL			0x3			/* PCI XINT4 routed to IRQ3 */

#define PCI_SLOT1_DEVNO			0x12		/* PCI SLOT 1 Device no */

#define MPC8266ADS_PCI_IRQ		08

#define PCI_INTA_IRQ			MPC8266ADS_PCI_IRQ
#define PCI_INTB_IRQ			MPC8266ADS_PCI_IRQ
#define PCI_INTC_IRQ			MPC8266ADS_PCI_IRQ
#define PCI_INTD_IRQ			MPC8266ADS_PCI_IRQ

#define PCI_IDSEL_BCM			22

#define PCI_XINT1_BCM			0x1
#define PCI_XINT2_BCM			0x2
#ifdef INSTALL_GCSA
#define PCI_XINT3_BCM			0xff
#elif defined(INSTALL_GCSD)
#define PCI_XINT3_BCM			0xb
#endif

#define PCI_LAT_TIMER			0x40		/* latency timer value, 64 PCI clocks */

#define PCI_CLINE_SZ			(_CACHE_ALIGN_SIZE / 4)

#define PCI1_DEV_ID				0x826010E3
#define PCI2_DEV_ID				0x826110E3
#define PCI3_DEV_ID				0x826210E3
#define PCI_DEV_ID_82XX			0x00031057	/* Id for MPC8266ADS-PCI board - Rev1 */
#define PCI_DEV_ID_85XX			0x000C1057	/* Id for MPC85xxADS-PCI board - Rev2 */
#define PCI_ID_I82559			0x12298086	/* Id for Intel 82559 */
#define PCI_ID_I82559ER			0x12098086	/* Id for Intel 82559 ER */
#define PCI_ID_BCM5616			0x561514E4	/* Id for BCM5616 */
#define PCI_ID_BCM5650			0x566514E4	/* Id for BCM5650 */
#define PCI_ID_BCM56504			0xB50414E4	/* Id for BCM56504 */
#define PCI_ID_BCM56580			0xB58014E4	/* Id for BCM56580 */

#define INTERRUPT_ROUTING_TABLE \
static UCHAR intLine [][4] = \
    { \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 0 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 1 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 2 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 3 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 4 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 5 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 6 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 7 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 8 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 9 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 10 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 11 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 12 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 13 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 14 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 15 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 16 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 17 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 18 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 19 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 20 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 21 */ \
        { PCI_XINT1_BCM,                                    \
                0xff, 0xff, 0xff },  /* device number 22 */ \
        { PCI_XINT2_BCM,                                    \
                0xff, 0xff, 0xff },  /* device number 23 */ \
        { PCI_XINT3_BCM,                                    \
                0xff, 0xff, 0xff },  /* device number 24 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 25 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 26 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 27 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 28 */ \
        { 0xff, 0xff, 0xff, 0xff },  /* device number 29 */ \
        { 0xff, 0xff, 0xff, 0xff }   /* device number 30 */ \
    };

#endif /* INCLUDE_PCI */

#define LBC_MEM_LOCAL_ADRS		0xe0000000
#define LBC_MEM_SIZE			0x10000000
#define LBC_ADRS_MASK			0xffff8000

#define LBC_CS1_ADRS			(LBC_MEM_LOCAL_ADRS | 0x00000000)
#define LBC_CS1_SIZE			0x04000000

#define LBC_CS2_ADRS			(LBC_MEM_LOCAL_ADRS | 0x04000000)
#define LBC_CS2_SIZE			0x04000000

#define LBC_CS4_ADRS			(LBC_MEM_LOCAL_ADRS | 0x08000000)
#define LBC_CS4_SIZE			0x00100000

#define LBC_CS5_ADRS			(LBC_MEM_LOCAL_ADRS | 0x09000000)
#define LBC_CS5_SIZE			0x00100000

#define LBC_CS6_ADRS			(LBC_MEM_LOCAL_ADRS | 0x0a000000)
#define LBC_CS6_SIZE			0x01000000

#define LBC_CS7_ADRS			(LBC_MEM_LOCAL_ADRS | 0x0b000000)
#define LBC_CS7_SIZE			0x01000000

/*
 * FLASH memory address space.
 */

#define FLASH0_MEM_ADRS			ROM_BASE_ADRS	/* Boot Loader stored here */
#define FLASH0_MEM_SIZE			ROM_SIZE		/* 512 KB FLASH0/PLCC seg */

#define INCLUDE_FLASH_MEM1