rominit.s

vxworks MPC8541 BSP

	mtctr   r6
delayLoop:
	bdnz    delayLoop

	/* Read LBC DLL and get tap reading */	
        lis     r6, HIADJ(M85XX_LBCDLLSR(CCSBAR))
        addi    r6, r6, LO(M85XX_LBCDLLSR(CCSBAR))
        lwz     r3, 0(r6)
	andi.   r3, r3, 0x7ff

	/* Start loop which terminates after ten cycles */
	li      r4, 11
retestLbcDll:
	addi    r4, r4, -1
	cmpwi   r4, 0

	/* terminate loop and generate check stop */
	beq     checkStop   
	/* Delay not more than 2500 CCB clock cycles */ 
	li      r5, 2000
	mtctr   r5
lbcDllDelay:
	bdnz    lbcDllDelay

	/* Read latest tap value */
        lwz     r8, 0(r6)
	andi.   r5, r8, 0x7ff

	/* diff between previous value */
	subf    r7, r5, r3
	/* Move latest value to previous */
	mr      r3, r5
	
	/* Check difference is not greater than 10 */	
	cmpwi   r7, 10
	bgt     retestLbcDll
	cmpwi   r7, -10
	blt     retestLbcDll

	/* Re-read dll reg and lock */
	lwz     r3, 0(r6)
        slwi    r3,r3,16
	lis     r5,0x8000
	or      r3,r3,r5
	stw     r3, 0(r6)

        isync
	sync
	mbar 0
	li      r4, 0x1
retestDll:	
	/* Read DDR DLL and test for override complete */	
        lis     r6, HI(M85XX_DDRDLLCR(CCSBAR))
        ori     r6, r6, LO(M85XX_DDRDLLCR(CCSBAR))
        lwz     r3, 0(r6)
	lis     r7, HI(0x81000100)
	ori     r7, r7 ,LO(0x81000100)
	cmpw    r7, r3
	beq     dllDone
	/* if override not complete reset DDR device and try again */
	lis     r6, HI(M85XX_DEVDISR(CCSBAR))
	ori     r6, r6, LO(M85XX_DEVDISR(CCSBAR))
	lwz     r3, 0(r6)
	oris    r3, r3, (M85XX_DEVDISR_DDR >> 16)
	stw     r3, 0(r6)
	mtctr   r4
dllDelay:
	nop
	bdnz    dllDelay
	lis     r6, HI(M85XX_DEVDISR(CCSBAR))
	ori     r6, r6, LO(M85XX_DEVDISR(CCSBAR))
	lwz     r7, 0(r6)
	lis	r8, HI(~M85XX_DEVDISR_DDR)
	ori	r8, r8, LO(~M85XX_DEVDISR_DDR)
	and     r7, r7, r8
	stw     r7, 0(r6)
	addi    r4, r4, 1
	b retestDll
dllDone:	
#ifdef INCLUDE_DDR_SDRAM
	/* Memory mapped region base address */
	
	WRITEADR(r6,r7,M85XX_LAWBAR0(CCSBAR), 
		 DDR_SDRAM_LOCAL_ADRS >> LAWBAR_ADRS_SHIFT)
	 
	WRITEADR(r6,r7,M85XX_LAWAR0(CCSBAR), 
		 LAWAR_ENABLE | LAWAR_TGTIF_DDRSDRAM | LAWAR_SIZE_256MB) 

        mbar 0
		
	/* Initialize the DDR Memory controller */
        lis	r6, HI(DDRBA)
        ori	r6, r6, LO(DDRBA)		/* r6 = DDR base */

	WRITEOFFSET(r6,r7,(CS0_BNDS), 0x0000000f)
	WRITEOFFSET(r6,r7,(CS1_BNDS), 0x00000000)
	WRITEOFFSET(r6,r7,(CS2_BNDS), 0x00000000)
	WRITEOFFSET(r6,r7,(CS3_BNDS), 0x00000000)
	WRITEOFFSET(r6,r7,(CS0_CONFIG), 0x80000102)
	WRITEOFFSET(r6,r7,(CS1_CONFIG), 0x00000000)
	WRITEOFFSET(r6,r7,(CS2_CONFIG), 0x00000000)
	WRITEOFFSET(r6,r7,(CS3_CONFIG), 0x00000000)
	
	WRITEOFFSET(r6,r7,(TIMING_CFG_1), 0x37344321)
	WRITEOFFSET(r6,r7,(TIMING_CFG_2), 0x00000800)
	WRITEOFFSET(r6,r7,(DDR_SDRAM_CFG), 0x42000000)
	WRITEOFFSET(r6,r7,(DDR_SDRAM_MODE_CFG), 0x00000062)
	WRITEOFFSET(r6,r7,(DDR_SDRAM_INTERVAL), 0x05200100)
#if 0
	WRITEOFFSET(r6,r7,(DDR_SDRAM_CLK_CNTL), 0x80000000)
#endif
	WRITEOFFSET(r6,r7,(DDR_SDRAM_CFG), 0xc2000000)

#ifdef INCLUDE_ECC
	WRITEOFFSET(r6,r7,(DDR_ERR_DISABLE), 0x00000000)
	WRITEOFFSET(r6,r7,(DDR_ERR_SBE), 0x00ff0000)
	isync
	sync
	mbar 0
	lis     r7, 0x1
	mtspr   9,  r7
eccDelayLoop:
	nop
	bdnz    eccDelayLoop
	WRITEOFFSET(r6,r7,(DDR_SDRAM_CFG), 0xe2000000)
#endif
	isync
	sync
	mbar 0
	
#endif /* INCLUDE_DDR_SDRAM */

	WRITEADR(r6,r7,M85XX_BR0(CCSBAR), ((FLASH0_MEM_ADRS & LBC_ADRS_MASK))     | 0x0801)
	WRITEADR(r6,r7,M85XX_OR0(CCSBAR),~((FLASH0_MEM_SIZE & LBC_ADRS_MASK) - 1) | 0x0647)

    mbar 0

	WRITEADR(r6,r7,M85XX_LAWBAR1(CCSBAR), \
	         (LBC_MEM_LOCAL_ADRS >> LAWBAR_ADRS_SHIFT))

	WRITEADR(r6,r7,M85XX_LAWAR1(CCSBAR),
		 (LAWAR_ENABLE | \
	          LAWAR_TGTIF_LBC | \
		  LAWAR_SIZE_256MB ))
        mbar 0

	WRITEADR(r6,r7,M85XX_OR1(CCSBAR),~((LBC_CS1_SIZE & LBC_ADRS_MASK) - 1) | 0x0667)
	WRITEADR(r6,r7,M85XX_BR1(CCSBAR), ((LBC_CS1_ADRS & LBC_ADRS_MASK))     | 0x1801)
	WRITEADR(r6,r7,M85XX_OR2(CCSBAR),~((LBC_CS2_SIZE & LBC_ADRS_MASK) - 1) | 0x0667)
	WRITEADR(r6,r7,M85XX_BR2(CCSBAR), ((LBC_CS2_ADRS & LBC_ADRS_MASK))     | 0x1801)
	WRITEADR(r6,r7,M85XX_OR4(CCSBAR),~((LBC_CS4_SIZE & LBC_ADRS_MASK) - 1) | 0x0e87)
	WRITEADR(r6,r7,M85XX_BR4(CCSBAR), ((LBC_CS4_ADRS & LBC_ADRS_MASK))     | 0x0801)
	WRITEADR(r6,r7,M85XX_OR5(CCSBAR),~((LBC_CS5_SIZE & LBC_ADRS_MASK) - 1) | 0x0e87)
	WRITEADR(r6,r7,M85XX_BR5(CCSBAR), ((LBC_CS5_ADRS & LBC_ADRS_MASK))     | 0x0801)
	WRITEADR(r6,r7,M85XX_OR6(CCSBAR),~((LBC_CS6_SIZE & LBC_ADRS_MASK) - 1) | 0x0ff7)
	WRITEADR(r6,r7,M85XX_BR6(CCSBAR), ((LBC_CS6_ADRS & LBC_ADRS_MASK))     | 0x0801)
#ifdef INSTALL_GCSA
	WRITEADR(r6,r7,M85XX_OR7(CCSBAR),~((LBC_CS7_SIZE & LBC_ADRS_MASK) - 1) | 0x0ff7)
	WRITEADR(r6,r7,M85XX_BR7(CCSBAR), ((LBC_CS7_ADRS & LBC_ADRS_MASK))     | 0x1001)
#elif defined(INSTALL_GCSD)
	WRITEADR(r6,r7,M85XX_OR7(CCSBAR),~((LBC_CS7_SIZE & LBC_ADRS_MASK) - 1) | 0x0ff7)
	WRITEADR(r6,r7,M85XX_BR7(CCSBAR), ((LBC_CS7_ADRS & LBC_ADRS_MASK))     | 0x0801)
#endif

    mbar 0

#ifdef INCLUDE_LBC_SDRAM
	/* Initialise SDRAM */
SdramInit:
	/* Memory mapped region base address */
	
	WRITEADR(r6,r7,M85XX_LAWBAR2(CCSBAR), \
	         (LBC_SDRAM_LOCAL_ADRS >> LAWBAR_ADRS_SHIFT) )

	WRITEADR(r6,r7,M85XX_LAWAR2(CCSBAR),
		 (LAWAR_ENABLE | \
	          LAWAR_TGTIF_LBC | \
		  LAWAR_SIZE_64MB ))
	
        mbar 0
 
	/* load OR3 */

	WRITEADR(r6,r7,M85XX_OR3 (CCSBAR), ~((LBC_SDRAM_LOCAL_SIZE & LBC_ADRS_MASK) - 1) | 0x6901)

	/* load BR3 */
	WRITEADR(r6,r7,M85XX_BR3 (CCSBAR), \
		 ((LBC_SDRAM_LOCAL_ADRS & LBC_ADRS_MASK)) | \
		 0x1861)

	/* Pre-charge all banks */
	WRITEADR(r6,r7,M85XX_LSDMR(CCSBAR),0x2863B723 )
 
	lis     r9,HIADJ(LBC_SDRAM_LOCAL_ADRS)
        addi    r9, r9, LO(LBC_SDRAM_LOCAL_ADRS)
 
	/* do a single write to an arbitrary location */

	addi    r5,0,0x00FF      /* Load 0x000000FF into r5 */
	stb     r5,0(r9)         /* Write 0xFF to SDRAM address - bits [24-31] */
	mbar 0
	/* issue a "Auto Refresh" command to SDRAM */

	WRITEADR(r6,r7,M85XX_LSDMR(CCSBAR),0x0863B723)
 
	/* do a single write to an arbitrary location */

	addi    r5,0,0x00FF      /* Load 0x000000FF into r5 */
	stb     r5,0(r9)         /* Write 0xFF to SDRAM address - bits [24-31] */
	mbar 0
	/* issue a "Auto Refresh" command to SDRAM */

	WRITEADR(r6,r7,M85XX_LSDMR(CCSBAR),0x0863B723)
 
	/* do a single write to an arbitrary location */

	addi    r8,0,0x00FF      /* Load 0x000000FF into r8 */

	stb     r8,0(r9)         /* Write 0xFF to address R9  */
	stb     r8,1(r9)         /* Write 0xFF to address R9  */
	stb     r8,2(r9)         /* Write 0xFF to address R9  */
	stb     r8,3(r9)         /* Write 0xFF to address R9  */
	stb     r8,4(r9)         /* Write 0xFF to address R9  */
	stb     r8,5(r9)         /* Write 0xFF to address R9  */
	stb     r8,6(r9)         /* Write 0xFF to address R9  */
	stb     r8,7(r9)         /* Write 0xFF to address R9  */
	
	/* issue a "Mode Register Write" command to SDRAM */

	WRITEADR(r6,r7,M85XX_LSDMR(CCSBAR),0x1863B723)
 
	/* do a single write to an arbitrary location */

	addi    r8,0,0x00FF      /* Load 0x000000FF into r8 */
	stb     r8,0(r9)         /* Write 0xFF to address R9 - bits [24-31] */

	/* enable refresh services and put SDRAM into normal operation  */
	
	WRITEADR(r6,r7,M85XX_LSDMR(CCSBAR),0x4063B723)

	/* program the MRTPR */

	addi    r5,0,TPR	 /* MRTPR[TPR] */
        lis     r6, HIADJ (M85XX_MRTPR (CCSBAR))
        addi    r6, r6, LO (M85XX_MRTPR (CCSBAR))
	sth     r5, 0x0 (r6)      /* store upper half-word */

	/* program the LSRT */

	addi    r5,0,0x20
        lis     r6, HIADJ (M85XX_LSRT (CCSBAR))
        addi    r6, r6, LO (M85XX_LSRT (CCSBAR))
	stb     r5, 0x0 (r6)      /* store byte - bits[24-31] */

	mbar 0

	lis     r9, HI(LBC_SDRAM_LOCAL_ADRS)
	ori     r9,r9, LO(LBC_SDRAM_LOCAL_ADRS)

	lis	r7, HIADJ(0x100)      /* Loop 256 times */
	addi    r7, r7, LO(0x100)
	mtspr	9,r7             /* Load spr CTR with 8 */
	lis 	r8,0x5555      /* Load 0x000000FF into r8 */
        ori     r8,r8,0x5555

SdramWrLoop2:
	
	stw  	r8,0(r9)        	/* Write 0xFF to address R9 */
	addi    r9,r9,4                 /* Move R9 to next byte */
	addi    r8,r8,1                 /* Add 1 to r8 */
	bc   	16,0,SdramWrLoop2	/* Decrement CTR, and possibly branch */
#endif  /* INCLUDE_LBC_SDRAM */

	/* Now that memory is stable we reset TLB entries for standard 
	 * operation 
	 */
	
        /*
         * TLB1 #0.  ROM - cached writethrough 0xff000000 -> 0xff000000.  
	 * 16MB
         * Attributes: SX/SW/SR **PROTECTED**
         */

        addis  r4,0,0x1000           /* TLBSEL = TLB1(CAM) , ESEL = 0 */ 
        ori    r4,r4,0x0000
        mtspr  MAS0, r4
        addis  r5,0,0xc000           /* V = 1, IPROT = 1, TID = 0*/
        ori    r5,r5,_MMU_TLB_SZ_16M  /* TS = 0, TSIZE = 16 MByte page size*/
        mtspr  MAS1, r5
        addis  r6,0,0xff00           /* EPN = 0xff000000*/
        ori    r6,r6,0x0016          /* WIMGE = 10110 */
        mtspr  MAS2, r6
        addis  r7,0,0xff00           /* RPN = 0xff000000*/
        ori    r7,r7,0x003f          /* Supervisor XWR*/
        mtspr  MAS3, r7
        tlbwe         
        tlbsync                     

        /*
         * TLB1 #1.  Main SDRAM - Cached
	 *           LOCAL_MEM_LOCAL_ADRS -> LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE
         * Attributes: UX/UW/UR/SX/SW/SR
         */

        addis  r4,0,0x1001           /* TLBSEL = TLB1(CAM) , ESEL = 1*/
        ori    r4,r4,0x0000
        mtspr  MAS0, r4
        addis  r5,0,0xc000           /* V = 1, IPROT = 1, TID = 0*/
        ori    r5,r5,_MMU_TLB_SZ_256M  /* TS = 0, TSIZE = 256 MByte page size*/
        mtspr  MAS1, r5
        addis  r6,0,HI(LOCAL_MEM_LOCAL_ADRS) /* EPN = LOCAL_MEM_LOCAL_ADRS */
        ori    r6,r6,0x0000          /* WIMGE = 00000 */
        mtspr  MAS2, r6
        addis  r7,0,HI(LOCAL_MEM_LOCAL_ADRS)  /* RPN = LOCAL_MEM_LOCAL_ADRS */
        ori    r7,r7,0x003f          /* User/Supervisor XWR*/
        mtspr  MAS3, r7
        tlbwe                       
        tlbsync                              

        /*
         * TLB1 #2.  CCSRBAR - guarded 0xfe000000 -> 0xfe000000.  
	 * 16MB
         * Attributes: SX/SW/SR
         */

        addis  r4,0,0x1002           /* TLBSEL = TLB1(CAM) , ESEL = 0 */ 
        ori    r4,r4,0x0000
        mtspr  MAS0, r4
        addis  r5,0,0x8000           /* V = 1, IPROT = 0, TID = 0*/
        ori    r5,r5,_MMU_TLB_SZ_16M  /* TS = 0, TSIZE = 16 MByte page size*/
        mtspr  MAS1, r5
        addis  r6,0,HI(CCSBAR)           /* EPN = 0xfe000000*/
        ori    r6,r6,0x0016          /* WIMGE = 11110 */
        mtspr  MAS2, r6
        addis  r7,0,HI(CCSBAR)           /* RPN = 0xfe000000*/
        ori    r7,r7,0x003f          /* Supervisor XWR*/
        mtspr  MAS3, r7
        tlbwe         
        tlbsync      
	               
        b  cold
checkStop:	
	ba 0x0				
FUNC_END(resetEntry)

#if   defined(_GNU_TOOL)
	.section .reset, "ax", @progbits
#elif defined(_DIAB_TOOL)
	.section .reset, 4, "rx"
#else
#error "Please add a correctly spelled .section directive for your toolchain."
#endif
FUNC_BEGIN(resetVector)
	b	resetEntry
FUNC_END(resetVector)