mottsecend.c

vxworks MPC8541 BSP

                               MOT_TSEC_MACCFG1_RESET_RX_MC  | 
                               MOT_TSEC_MACCFG1_RESET_TX_MC  | 
                               MOT_TSEC_MACCFG1_RESET_RX_FUN | 
                               MOT_TSEC_MACCFG1_RESET_TX_FUN) ;

    MOT_TSEC_MS_DELAY(16);

    intUnlock(intLevel);

    }

/*******************************************************************************
*
* motTsecRestart - Restarts device after motTsecGracefulStop
*
* This routine restarts the ethernet device after a motTsecGracefulStop event.
*
* RETURNS:
*
* ERRNO
*/
LOCAL void motTsecRestart
    (
    TSEC_DRV_CTRL * pDrvCtrl
    )
    {
    TSEC_REG_T *tsecReg = pDrvCtrl->tsecRegsPtr;
    volatile int rstatVal,tstatVal,ieventVal;
    int intLevel;

    tstatVal = MOT_TSEC_TSTAT_REG;
    MOT_TSEC_TSTAT_REG = tstatVal;

    rstatVal = MOT_TSEC_RSTAT_REG;
    MOT_TSEC_RSTAT_REG = rstatVal;

    ieventVal = MOT_TSEC_IEVENT_REG;
    MOT_TSEC_IEVENT_REG = ieventVal;
    ieventVal = MOT_TSEC_IEVENT_REG;

    MOT_TSEC_RBASE_REG  = (UINT32) pDrvCtrl->pRbdBase;
    MOT_TSEC_TBASE_REG  = (UINT32) pDrvCtrl->pTbdBase;

    pDrvCtrl->rbdIndex = 0;
    pDrvCtrl->tbdIndex = 0;

    /* Initialize the transmit buffer descriptors */

    if (motTsecTbdInit(pDrvCtrl) == ERROR)
        {
        printf("motTsecTbdInit failed in Restart \n");
        /* return ERROR; */
        }

    /* Initialize the receive buffer descriptors */

    if (motTsecRbdInit(pDrvCtrl) == ERROR)
        {
        printf("motTsecRbdInit failed in Restart \n");
        /* return ERROR; */
        }

    intLevel = intLock();

    /* Enable Transmit and Receive */
    MOT_TSEC_MACCFG1_REG |= (MOT_TSEC_MACCFG1_RX_EN | MOT_TSEC_MACCFG1_TX_EN);

    /* This delay is required by the hardware */
    MOT_TSEC_MS_DELAY(16);

    /* Ensure graceful stop rx and tx isn't set */

    MOT_TSEC_DMACTRL_REG &= (~(MOT_TSEC_DMACTRL_GTS | MOT_TSEC_DMACTRL_GRS));

    MOT_TSEC_MS_DELAY(16);
    intUnlock(intLevel);

    }

/***************************************************************************
*
* motTsecParmInit - initializes motTsec environment parameters
*
* This routine initializes the motTsec environment parameters.
*
* RETURNS: OK or ERROR
*
* ERRNO
*/
LOCAL STATUS motTsecParmInit
    (
    TSEC_DRV_CTRL * pDrvCtrl
    )
    {
    int      i;
    UINT32   flags;
    UINT16   phyData;
    UINT32   maccfg1Reg;
    UINT32   maccfg2Reg;
    UINT32   ecntrlReg;
    UINT32   rctrlReg;
    UINT32   tctrlReg;
    UINT32   dmactrlReg;
   /* UINT32   edisReg;
    UINT32   tstatReg;*/
    UINT32   txicReg;
    UINT32   rstatReg; 
    UINT32   mrblrReg;
    UINT32   ptvReg;
  /*  UINT32   tbipaReg;*/
    UINT32   fifoTxThrReg;
    UINT32   fifoTxStarveReg;
    UINT32   fifoTxStarveShutoffReg;
    UINT32   minflrReg;
    UINT32   hafdupReg;
    UINT32   ipgifgReg;
    UINT32   maxfrmReg;
    UINT32   ifstatReg;
    UINT32   attrReg;
    UINT32   attreliReg;
    UINT32   miicfgReg;
  /*  UINT32   miicomReg;*/
    UINT32   macIndividualHashReg[8];
    UINT32   macGroupHashReg[8];
    TSEC_REG_T * tsecMiiReg = pDrvCtrl->tsecMiiPtr;

    MOT_TSEC_FRAME_SET(pDrvCtrl);

    /* Set and clear MACCFG1 to perform a soft reset on all modules */
    /* set up TSEC register defaults */
    maccfg1Reg = MOT_TSEC_MACCFG1_DEFAULT;

    ifstatReg  = MOT_TSEC_IFSTAT_DEFAULT;
 /*   edisReg    = MOT_TSEC_EDIS_DEFAULT;*/
    dmactrlReg = MOT_TSEC_DMACTRL_DEFAULT; 
    tctrlReg   = MOT_TSEC_TCTRL_DEFAULT;
    txicReg    = MOT_TSEC_TXIC_DEFAULT; 
  /*  tstatReg   = MOT_TSEC_TSTAT_DEFAULT;*/
    rstatReg   = MOT_TSEC_RSTAT_DEFAULT;
    mrblrReg   = MOT_TSEC_MRBLR_DEFAULT;
    ptvReg     = MOT_TSEC_PVT_DEFAULT;
   /* tbipaReg   = MOT_TSEC_TBIPA_DEFAULT;*/
    minflrReg  = MOT_TSEC_MINFLR_DEFAULT;
    hafdupReg  = MOT_TSEC_HAFDUP_DEFAULT;
    ipgifgReg  = MOT_TSEC_IPGIFG_DEFAULT;
    maxfrmReg  = MOT_TSEC_MAXFRM_DEFAULT;
    miicfgReg  = MOT_TSEC_MIICFG_DEFAULT;
 /*   miicomReg  = MOT_TSEC_MIICOM_DEFAULT;*/
    attrReg    = MOT_TSEC_ATTR_DEFAULT;
    attreliReg = MOT_TSEC_ATTRELI_EL_DEFAULT;

    fifoTxThrReg    = MOT_TSEC_FIFO_TX_THR_DEFAULT;
    fifoTxStarveReg = MOT_TSEC_FIFO_TX_STARVE_DEFAULT;
    fifoTxStarveShutoffReg = MOT_TSEC_FIFO_TX_STARVE_OFF_DEFAULT;

    for (i = 0; i < 8; i++)
        {
        macIndividualHashReg[i] = 0;
        macGroupHashReg[i]      = 0;
        }

    /* prepare to set the driver's initial operating mode */
    maccfg2Reg = MOT_TSEC_MACCFG2_DEFAULT;
    ecntrlReg  = MOT_TSEC_ECNTRL_DEFAULT;
    rctrlReg   = MOT_TSEC_RCTRL_DEFAULT;

    MOT_TSEC_LOG (MOT_TSEC_DBG_START,"TSEC MODE: %d\n",
                 pDrvCtrl->userFlags,2,3,4,5,6);

    /* switch ((UINT32)(pDrvCtrl->userFlags)) */
    switch ((UINT32)(pDrvCtrl->userFlags & MOT_TSEC_USR_MODE_MASK))
        {
        /* default to the defines in motTsecEnd.h */
        case MOT_TSEC_USR_MODE_DEFAULT:
            break;

        case MOT_TSEC_USR_MODE_TBI:
            ecntrlReg  |= MOT_TSEC_ECNTRL_TBIM;
            maccfg2Reg &= 
                      ~MOT_TSEC_MACCFG2_IF_MODE(MOT_TSEC_MACCFG2_IF_MODE_MASK);

            maccfg2Reg |= MOT_TSEC_MACCFG2_FULL_DUPLEX |
                MOT_TSEC_MACCFG2_IF_MODE(MOT_TSEC_MACCFG2_IF_MODE_GMII_TBI);

            break;

        case MOT_TSEC_USR_MODE_RTBI:
            ecntrlReg  |= MOT_TSEC_ECNTRL_TBIM | MOT_TSEC_ECNTRL_RPM;
            maccfg2Reg &= 
                      ~MOT_TSEC_MACCFG2_IF_MODE(MOT_TSEC_MACCFG2_IF_MODE_MASK);

            maccfg2Reg |= MOT_TSEC_MACCFG2_FULL_DUPLEX |
                MOT_TSEC_MACCFG2_IF_MODE(MOT_TSEC_MACCFG2_IF_MODE_GMII_TBI);

            break;
        case MOT_TSEC_USR_MODE_MII:
            maccfg2Reg &= 
                      ~MOT_TSEC_MACCFG2_IF_MODE(MOT_TSEC_MACCFG2_IF_MODE_MASK);
            maccfg2Reg |= MOT_TSEC_MACCFG2_FULL_DUPLEX | 
                      MOT_TSEC_MACCFG2_IF_MODE(MOT_TSEC_MACCFG2_IF_MODE_MII);

            motTsecMiiPhyRead (pDrvCtrl, pDrvCtrl->phyInfo->phyAddr, 0x0, 
                               &phyData);
            phyData |= 0x1000;
            motTsecMiiPhyWrite (pDrvCtrl, pDrvCtrl->phyInfo->phyAddr, 0x0, 
                                phyData);

            motTsecMiiPhyRead (pDrvCtrl, pDrvCtrl->phyInfo->phyAddr, 0x0, 
                               &phyData);

            break;

        case MOT_TSEC_USR_MODE_GMII:
            maccfg2Reg &= MOT_TSEC_MACCFG2_FULL_DUPLEX | 
                      ~MOT_TSEC_MACCFG2_IF_MODE(MOT_TSEC_MACCFG2_IF_MODE_MASK);

            maccfg2Reg |= MOT_TSEC_MACCFG2_FULL_DUPLEX |
                MOT_TSEC_MACCFG2_IF_MODE(MOT_TSEC_MACCFG2_IF_MODE_GMII_TBI);

            break;

        case MOT_TSEC_USR_MODE_RGMII:
            ecntrlReg  |= MOT_TSEC_ECNTRL_RPM;
            maccfg2Reg &= 
                      ~MOT_TSEC_MACCFG2_IF_MODE(MOT_TSEC_MACCFG2_IF_MODE_MASK);

            maccfg2Reg |= MOT_TSEC_MACCFG2_FULL_DUPLEX |
                MOT_TSEC_MACCFG2_IF_MODE(MOT_TSEC_MACCFG2_IF_MODE_GMII_TBI);

            break;

        case MOT_TSEC_USR_MODE_RGMII_10:
            ecntrlReg  |= MOT_TSEC_ECNTRL_RPM;
            maccfg2Reg &= 
                      ~MOT_TSEC_MACCFG2_IF_MODE(MOT_TSEC_MACCFG2_IF_MODE_MASK);

            maccfg2Reg |= MOT_TSEC_MACCFG2_FULL_DUPLEX |
                MOT_TSEC_MACCFG2_IF_MODE(MOT_TSEC_MACCFG2_IF_MODE_GMII_TBI);

            break;

        case MOT_TSEC_USR_MODE_RGMII_100:
            ecntrlReg  |= MOT_TSEC_ECNTRL_RPM | MOT_TSEC_ECNTRL_R100M;
            maccfg2Reg &= 
                      ~MOT_TSEC_MACCFG2_IF_MODE(MOT_TSEC_MACCFG2_IF_MODE_MASK);

            maccfg2Reg |= MOT_TSEC_MACCFG2_FULL_DUPLEX |
                MOT_TSEC_MACCFG2_IF_MODE(MOT_TSEC_MACCFG2_IF_MODE_GMII_TBI);

            break;

        default:
            break;
        }
    /* initialize the extended TSEC parameters */
    if (pDrvCtrl->initParmsExt)
        {
        flags = pDrvCtrl->initParmsExt->usrRegFlags;
        /* Individual MAC hash table */
        if (flags & MOT_TSEC_FLAG_IADDR)
            {
            macIndividualHashReg[0] = 
                                   pDrvCtrl->initParmsExt->macIndividualHash[0];

            macIndividualHashReg[1] = 
                                   pDrvCtrl->initParmsExt->macIndividualHash[1];

            macIndividualHashReg[2] = 
                                   pDrvCtrl->initParmsExt->macIndividualHash[2];

            macIndividualHashReg[3] = 
                                   pDrvCtrl->initParmsExt->macIndividualHash[3];

            macIndividualHashReg[4] = 
                                   pDrvCtrl->initParmsExt->macIndividualHash[4];

            macIndividualHashReg[5] = 
                                   pDrvCtrl->initParmsExt->macIndividualHash[5];

            macIndividualHashReg[6] = 
                                   pDrvCtrl->initParmsExt->macIndividualHash[6];

            macIndividualHashReg[7] = 
                                   pDrvCtrl->initParmsExt->macIndividualHash[7];
            }

        /* Group MAC hash table */

        if (flags & MOT_TSEC_FLAG_GADDR)
            {
            macGroupHashReg[0] = pDrvCtrl->initParmsExt->macGroupHash[0];
            macGroupHashReg[1] = pDrvCtrl->initParmsExt->macGroupHash[1];
            macGroupHashReg[2] = pDrvCtrl->initParmsExt->macGroupHash[2];
            macGroupHashReg[3] = pDrvCtrl->initParmsExt->macGroupHash[3];
            macGroupHashReg[4] = pDrvCtrl->initParmsExt->macGroupHash[4];
            macGroupHashReg[5] = pDrvCtrl->initParmsExt->macGroupHash[5];
            macGroupHashReg[6] = pDrvCtrl->initParmsExt->macGroupHash[6];
            macGroupHashReg[7] = pDrvCtrl->initParmsExt->macGroupHash[7];
            }
        }


    /* write all configured registers */
    MOT_TSEC_MACCFG2_REG = maccfg2Reg;

    MOT_TSEC_ECNTRL_REG  = ecntrlReg;

    /* individual MAC hash table */

    for (i = 0; i < 8; i++)
        MOT_TSEC_IADDR_REG[i] = macIndividualHashReg[i];

    /* Group MAC hash table */

    for (i = 0; i < 8; i++)
        MOT_TSEC_GADDR_REG[i] = macGroupHashReg[i];

    /* set the  ethernet address in the TSEC */
    motTsecAddrSet (pDrvCtrl, (char *)&pDrvCtrl->enetAddr);

    MOT_TSEC_RCTRL_REG   = rctrlReg;

    MOT_TSEC_TBIPA_REG   = MOT_TSEC_TBIPA_DEFAULT;

    pDrvCtrl->tbiAdr     = MOT_TSEC_TBIPA_DEFAULT + pDrvCtrl->unit;
    MOT_TSEC_TBIPA_REG   = pDrvCtrl->tbiAdr;
    MOT_TSEC_MIIMCFG_REG = miicfgReg; 

    /* clear mask and any events pending */
    MOT_TSEC_IMASK_REG  = 0;
    MOT_TSEC_IEVENT_REG = 0xffffffff;

    /* no error events */
    MOT_TSEC_EDIS_REG   = 0xffffffff;

    MOT_TSEC_DMACTRL_REG = dmactrlReg;
    MOT_TSEC_TCTRL_REG   = tctrlReg;
    MOT_TSEC_TXIC_REG    = txicReg; 
    MOT_TSEC_RSTAT_REG   = rstatReg;
    MOT_TSEC_MRBLR_REG   = mrblrReg;
    MOT_TSEC_PTV_REG     = ptvReg;
    MOT_TSEC_MINFLR_REG  = minflrReg;
    MOT_TSEC_HAFDUP_REG  = hafdupReg;
    MOT_TSEC_IPGIFG_REG  = ipgifgReg;
    MOT_TSEC_MAXFRM_REG  = maxfrmReg;
    MOT_TSEC_IFSTAT_REG  = ifstatReg;
    MOT_TSEC_FIFO_TX_THR_REG = fifoTxThrReg;
    MOT_TSEC_FIFO_TX_STARVE_REG = fifoTxStarveReg;
    MOT_TSEC_FIFO_TX_STARVE_SHUTOFF_REG = fifoTxStarveShutoffReg;

    MOT_TSEC_ATTR_REG  = attrReg;
    MOT_TSEC_ATTRE