umc_vc1_common_defs.h

audio-video-codecs.rar语音编解码器

/* /////////////////////////////////////////////////////////////////////////////
/* /////////////////////////////////////////////////////////////////////////////
//
//                  INTEL CORPORATION PROPRIETARY INFORMATION
//     This software is supplied under the terms of a license agreement or
//     nondisclosure agreement with Intel Corporation and may not be copied
//     or disclosed except in accordance with the terms of that agreement.
//          Copyright(c) 2004-2007 Intel Corporation. All Rights Reserved.
//
//
//          VC-1 (VC1) decoder, Coded block pattern tables
//
*/

#include "umc_defs.h"

#if defined (UMC_ENABLE_VC1_VIDEO_DECODER) || defined (UMC_ENABLE_VC1_SPLITTER) || defined (UMC_ENABLE_VC1_VIDEO_ENCODER)

#ifndef __UMC_VC1_COMMON_DEFS_H__
#define __UMC_VC1_COMMON_DEFS_H__

#include <stdio.h>
#include "ippi.h"
#include "ippvc.h"
#include "umc_vc1_common_macros_defs.h"


//#define _OWN_FUNCTION

#define VC1_ENC_RECODING_MAX_NUM 3
#define START_CODE_NUMBER 600

typedef enum
{
    VC1_ERR_NOSIGNAL = 0,
    VC1_ERR_SIGNAL   = 1

} VC1_ERROR;

#define VC1_SIGNAL     0
#define VC1_DEC_ERR(value) (value & VC1_ERR_SIGNAL)

typedef enum
{
    VC1_OK   = 0,
    VC1_FAIL = 1,
    VC1_SKIP_FRAME = 2,
    VC1_NOT_ENOUGH_DATA = -996,
    VC1_WRN_INVALID_STREAM = 3
}VC1Status;


// start code (for vc1 format)
//see C24.008-VC1-Spec-CD2r1.pdf standard Annex E,E5, p. 431
typedef enum
{
    VC1_EndOfSequence              = 0x0A,
    VC1_Slice                      = 0x0B,
    VC1_Field                      = 0x0C,
    VC1_FrameHeader                = 0x0D,
    VC1_EntryPointHeader           = 0x0E,
    VC1_SequenceHeader             = 0x0F,
    VC1_SliceLevelUserData         = 0x1B,
    VC1_FieldLevelUserData         = 0x1C,
    VC1_FrameLevelUserData         = 0x1D,
    VC1_EntryPointLevelUserData    = 0x1E,
    VC1_SequenceLevelUserData      = 0x1F
} VC1StartCode;

//input file format
enum
{
    RCVFileFormat               = 0,
    VC1FileFormat               = 1,
    VC1_UnknownFileFormat       = 10
};


//frame coding mode
enum
{
    VC1_Progressive           = 0,
    VC1_FrameInterlace        = 1,
    VC1_FieldInterlace        = 2
};

enum
{
    VC1_I_FRAME = 0,
    VC1_P_FRAME = 1,
    VC1_B_FRAME = 2,
    VC1_BI_FRAME= 3,
    VC1_SKIPPED_FRAME = 4
};
#define VC1_IS_REFERENCE(value) ((value < VC1_B_FRAME)||(value == VC1_SKIPPED_FRAME))
#define VC1_IS_NOT_PRED(value) ((value == VC1_I_FRAME)||(value == VC1_BI_FRAME))
#define VC1_IS_PRED(value) ((value == VC1_P_FRAME)||(value == VC1_B_FRAME))


enum
{
    VC1_COND_OVER_FLAG_NONE = 0, //no 8x8 block boundaries are smoothed,
                             //see standart, p163
    VC1_COND_OVER_FLAG_ALL = 2,  //all 8x8 block boundaries are smoothed,
                             //see standart, p163
    VC1_COND_OVER_FLAG_SOME = 3  //some 8x8 block boundaries are smoothed,
                             //see standart, p163
};
#define VC1_MAX_BITPANE_CHUNCKS 7
#define VC1_NUM_OF_BLOCKS 6
#define VC1_NUM_OF_LUMA   4
#define VC1_PIXEL_IN_LUMA 16
#define VC1_PIXEL_IN_CHROMA 8
#define VC1_PIXEL_IN_BLOCK  8

enum
{
    VC1_BLK_INTER8X8   = 0x1,
    VC1_BLK_INTER8X4   = 0x2,
    VC1_BLK_INTER4X8   = 0x4,
    VC1_BLK_INTER4X4   = 0x8,
    VC1_BLK_INTER      = 0xf,
    VC1_BLK_INTRA_TOP  = 0x10,
    VC1_BLK_INTRA_LEFT = 0x20,
    VC1_BLK_INTRA      = 0x30
};

#define VC1_IS_BLKINTRA(value) (value & 0x30)
enum
{
    VC1_MB_INTRA             = 0x0,
    VC1_MB_1MV_INTER         = 0x1,
    VC1_MB_2MV_INTER         = 0x2,
    VC1_MB_4MV_INTER         = 0x3,
    VC1_MB_4MV_FIELD_INTER   = 0x4,
    VC1_MB_DIRECT            = 0x0,
    VC1_MB_FORWARD           = 0x8,
    VC1_MB_BACKWARD          = 0x10,
    VC1_MB_INTERP            = 0x18
 };

#define VC1_IS_MVFIELD(value)  (((value&7) == VC1_MB_2MV_INTER)||((value&7) == VC1_MB_4MV_FIELD_INTER ))
#define VC1_GET_MBTYPE(value)  (value&7)
#define VC1_GET_PREDICT(value) (value&56)

#define VC1MBQUANT 2
#define VC1SLICEINPARAL 512
//#define VC1MBALLOCSIZE 1024
#define VC1FRAMEPARALLELPAIR 1
//#define CREATE_ES
//#define VC1_THREAD_STATISTIC

enum
{
    VC1_MVMODE_HPELBI_1MV    = 0,    //0000      1 MV Half-pel bilinear
    VC1_MVMODE_1MV           = 1,    //1         1 MV
    VC1_MVMODE_MIXED_MV      = 2,    //01        Mixed MV
    VC1_MVMODE_HPEL_1MV      = 3,    //001       1 MV Half-pel
    VC1_MVMODE_INTENSCOMP    = 4,    //0001      Intensity Compensation
};

enum
{
    VC1_DQPROFILE_ALL4EDGES  = 0,    //00    All four Edges
    VC1_DQPROFILE_DBLEDGES   = 1,    //01    Double Edges
    VC1_DQPROFILE_SNGLEDGES  = 2,    //10    Single Edges
    VC1_DQPROFILE_ALLMBLKS   = 3     //11    All Macroblocks
};
enum
{
    VC1_ALTPQUANT_LEFT            = 1,
    VC1_ALTPQUANT_TOP             = 2,
    VC1_ALTPQUANT_RIGTHT          = 4,
    VC1_ALTPQUANT_BOTTOM          = 8,
    VC1_ALTPQUANT_LEFT_TOP        = 3,
    VC1_ALTPQUANT_TOP_RIGTHT      = 6,
    VC1_ALTPQUANT_RIGTHT_BOTTOM   = 12,
    VC1_ALTPQUANT_BOTTOM_LEFT     = 9,
    VC1_ALTPQUANT_EDGES           = 15,
    VC1_ALTPQUANT_ALL             = 16,
    VC1_ALTPQUANT_NO              = 0,
    VC1_ALTPQUANT_MB_LEVEL        = 32,
    VC1_ALTPQUANT_ANY_VALUE       = 64
};
enum //profile definitions
{
    VC1_PROFILE_SIMPLE = 0, //disables X8 Intraframe, Loop filter, DQuant, and
                            //Multires while enabling the Fast Transform
    VC1_PROFILE_MAIN   = 1, //The main profile is has all the simple profile
                            //tools plus loop filter, dquant, and multires
    VC1_PROFILE_RESERVED = 2,
    VC1_PROFILE_ADVANCED= 3    //The complex profile has X8 Intraframe can use
                      //the normal IDCT transform or the VC1 Inverse Transform
};

enum //bitplane modes definitions
{
    VC1_BITPLANE_RAW_MODE        = 0,//Raw           0000
    VC1_BITPLANE_NORM2_MODE      = 1,//Norm-2        10
    VC1_BITPLANE_DIFF2_MODE      = 2,//Diff-2        001
    VC1_BITPLANE_NORM6_MODE      = 3,//Norm-6        11
    VC1_BITPLANE_DIFF6_MODE      = 4,//Diff-6        0001
    VC1_BITPLANE_ROWSKIP_MODE    = 5,//Rowskip       010
    VC1_BITPLANE_COLSKIP_MODE    = 6 //Colskip       011
};

#define VC1_UNDEF_PQUANT 0
#define VC1_MVINTRA (0X7F7F)

enum //quantizer deadzone definitions
{
    VC1_QUANTIZER_UNIFORM    = 0,
    VC1_QUANTIZER_NONUNIFORM = 1
};

enum //prediction directions definitions
{
    VC1_ESCAPEMODE3_Conservative    = 0,
    VC1_ESCAPEMODE3_Efficient       = 1
};
//for subBlockPattern (numCoef)
enum
{
    VC1_SBP_0               = 0x8,
    VC1_SBP_1               = 0x4,
    VC1_SBP_2               = 0x2,
    VC1_SBP_3               = 0x1
};

//interlace frame
//field/frame transform
enum
{
    VC1_FRAME_TRANSFORM = 0,
    VC1_FIELD_TRANSFORM = 1,
    VC1_NO_CBP_TRANSFORM,
    VC1_NA_TRANSFORM
};

enum
{
    VC1_SBP_8X8_BLK          = 0,
    VC1_SBP_8X4_BOTTOM_BLK   = 1,
    VC1_SBP_8X4_TOP_BLK      = 2,
    VC1_SBP_8X4_BOTH_BLK     = 3,
    VC1_SBP_4X8_RIGHT_BLK    = 4,
    VC1_SBP_4X8_LEFT_BLK     = 5,
    VC1_SBP_4X8_BOTH_BLK     = 6,
    VC1_SBP_4X4_BLK          = 7,

    VC1_SBP_8X8_MB        = 8,
    VC1_SBP_8X4_BOTTOM_MB = 9,
    VC1_SBP_8X4_TOP_MB    = 10,
    VC1_SBP_8X4_BOTH_MB   = 11,
    VC1_SBP_4X8_RIGHT_MB  = 12,
    VC1_SBP_4X8_LEFT_MB   = 13,
    VC1_SBP_4X8_BOTH_MB   = 14,
    VC1_SBP_4X4_MB        = 15
};

//for LeftTopRightPositionFlag
enum
{
    VC1_COMMON_MB       = 0x000,
    VC1_LEFT_MB         = 0xA00,
    VC1_TOP_LEFT_MB     = 0xAC0,
    VC1_TOP_LEFT_RIGHT  = 0xAC5,
    VC1_LEFT_RIGHT_MB   = 0xA05,
    VC1_TOP_MB          = 0x0C0,
    VC1_TOP_RIGHT_MB    = 0x0C5,
    VC1_RIGHT_MB        = 0x005
};

#define VC1_IS_NO_LEFT_MB(value)  !(value&0x800)
#define VC1_IS_NO_TOP_MB(value)   !(value&0x80)
#define VC1_IS_NO_RIGHT_MB(value) (!(value&0x01))

//only left
#define VC1_IS_LEFT_MB(value)  (value&0x800)&&(!(value&0x80)) && (!(value&0x1))
//only top
#define VC1_IS_TOP_MB(value)(value&0x80)&&(!(value&0x800))&&(!(value&0x1))
//only right
#define VC1_IS_RIGHT_MB(value)  (value&0x01)&&(!(value&0x800))&&(!(value&0x80))
//left and top
#define VC1_IS_LEFT_TOP_MB(value)    (value&0x800)&&(value&0x80)&&(!(value&0x1))
#define VC1_IS_TOP_RIGHT_MB(value)   (value&0x80)&&(value&0x1)&&(!(value&0x800))

#define VC1_IS_LEFT_RIGHT_MB(value)  (value&0x800)&&(value&0x1)&&(!(value&0x80))
//#define VC1_IS_NOT_TOP_LEFT_MB(value) (!(value&0x80))&&(!(value&0x800))

//for IntraFlag
enum
{
    VC1_All_INTRA        = 0x3F,
    VC1_BLOCK_0_INTRA    = 0x01,
    VC1_BLOCK_1_INTRA    = 0x02,
    VC1_BLOCK_2_INTRA    = 0x04,
    VC1_BLOCK_3_INTRA    = 0x08,
    VC1_BLOCK_4_INTRA    = 0x10,
    VC1_BLOCKS_0_1_INTRA = 0x03,
    VC1_BLOCKS_2_3_INTRA = 0x0C,
    VC1_BLOCKS_0_2_INTRA = 0x05,
    VC1_BLOCKS_1_3_INTRA = 0x0A
};

//for smoothing
#define VC1_EDGE_MB(intraflag, value)  ((intraflag&value)==value)


#define VC1_IS_INTER_MB(value)  ((value == 0x00)||(value == 0x01)||(value == 0x02)||(value == 0x04)||(value == 0x08))

//for extended differantial MV range flag(inerlace P picture)
enum
{
    VC1_DMVRANGE_NONE = 0,
    VC1_DMVRANGE_HORIZONTAL_RANGE,
    VC1_DMVRANGE_VERTICAL_RANGE,
    VC1_DMVRANGE_HORIZONTAL_VERTICAL_RANGE
};


//intensity comprnsation
enum
{
    VC1_INTCOMP_TOP_FIELD    = 1,
    VC1_INTCOMP_BOTTOM_FIELD = 2,
    VC1_INTCOMP_BOTH_FIELD   = 3
};

#define VC1_IS_INT_TOP_FIELD(value)    (value & VC1_INTCOMP_TOP_FIELD)
#define VC1_IS_INT_BOTTOM_FIELD(value) (value & VC1_INTCOMP_BOTTOM_FIELD)
#define VC1_IS_INT_BOTH_FIELD(value)   (value & VC1_INTCOMP_BOTH_FIELD)

#define VC1_BRACTION_INVALID 0
#define VC1_BRACTION_BI 9


#define VC1_PADDING_SIZE       64
#define VC1_HORIZONTAL_PADDING 64


#define VC1_MAX_SLICE_NUM  512

typedef struct
{
    Ipp32s*             pRLTable;
    const Ipp8s*        pDeltaLevelLast0;
    const Ipp8s*        pDeltaLevelLast1;
    const Ipp8s*        pDeltaRunLast0;
    const Ipp8s*        pDeltaRunLast1;
}IppiACDecodeSet_VC1;


#define VC1_IS_BITPLANE_RAW_MODE(bitplane) ((bitplane)->m_imode == VC1_BITPLANE_RAW_MODE)
#define VC1_IS_U_PRESENT_IN_CBPCY(value) (value & 2)
#define VC1_IS_V_PRESENT_IN_CBPCY(value) (value & 1)

#define VC1_NEXT_BITS(num_bits, value) VC1NextNBits(pContext->m_bitstream.pBitstream, pContext->m_bitstream.bitOffset, num_bits, value);
#define VC1_GET_BITS(num_bits, value)  VC1GetNBits(pContext->m_bitstream.pBitstream, pContext->m_bitstream.bitOffset, num_bits, value);

typedef struct
{
   Ipp32u HRD_NUM_LEAKY_BUCKETS; //5
   Ipp32u BIT_RATE_EXPONENT;     //4
   Ipp32u BUFFER_SIZE_EXPONENT;  //4

   // 32 - max size see Standard, p32
   Ipp32u HRD_RATE[32];      //16
   Ipp32u HRD_BUFFER[32];    //16
   Ipp32u HRD_FULLNESS[32];  //16
}VC1_HRD_PARAMS;

typedef struct
{
    Ipp8u              m_invert;
    Ipp32s             m_imode;
    Ipp8u*             m_databits;
}VC1Bitplane;

typedef struct
{
    //common field
    Ipp32u PROFILE;            //2

    //Advanced profile fields
    Ipp32u LEVEL;              //3
  //  Ipp32u CHROMAFORMAT;     //2

    //common fields
    Ipp32u FRMRTQ_POSTPROC;  //3
    Ipp32u BITRTQ_POSTPROC;  //5

    //Advanced profile fields
    Ipp32u POSTPROCFLAG;      //1
    Ipp32u MAX_CODED_WIDTH;   //12
    Ipp32u MAX_CODED_HEIGHT;  //12
    Ipp32u PULLDOWN;          //1
    Ipp32u INTERLACE;         //1
    Ipp32u TFCNTRFLAG;        //1

    //Simple/Main profile fields
    Ipp32u LOOPFILTER;       //1 uimsbf
    Ipp32u MULTIRES;         //1 uimsbf
    Ipp32u FASTUVMC;         //1 uimsbf
    Ipp32u EXTENDED_MV;      //1 uimsbf
    Ipp32u DQUANT;           //2 uimsbf
    Ipp32u VSTRANSFORM;      //1 uimsbf
    Ipp32u OVERLAP;          //1 uimsbf
    Ipp32u SYNCMARKER;       //1 uimsbf
    Ipp32u RANGERED;         //1 uimsbf
    Ipp32u MAXBFRAMES;       //3 uimsbf
    Ipp32u QUANTIZER;        //2 uimsbf

    //common fields
    Ipp32u FINTERPFLAG;        //1
    //Ipp32u DISPLAY_EXT;        //1
    Ipp32u HRD_PARAM_FLAG;     //1

    //HRD PARAMS
   Ipp32u HRD_NUM_LEAKY_BUCKETS; //5
   //Ipp32u BIT_RATE_EXPONENT;     //4
   //Ipp32u BUFFER_SIZE_EXPONENT;  //4

   // 32 - max size see Standard, p32
 //  Ipp32u HRD_RATE[32];   //16
 //  Ipp32u HRD_BUFFER[32]; //16

   //Ipp8u m_ubRoundCtl;

    Ipp16u widthMB;
    Ipp16u heightMB;

//entry point
    Ipp32u BROKEN_LINK;
    Ipp32u CLOSED_ENTRY;
    Ipp32u PANSCAN_FLAG;
    Ipp32u REFDIST_FLAG;

    Ipp32u CODED_WIDTH;
    Ipp32u CODED_HEIGHT;
    Ipp32u EXTENDED_DMV;
    Ipp32u RANGE_MAPY_FLAG;
    Ipp32s RANGE_MAPY;
    Ipp32u RANGE_MAPUV_FLAG;
    Ipp32s RANGE_MAPUV;
    Ipp32u RNDCTRL;     // 1 rounding control bit


#ifdef DXVA_SIM
    Ipp32u RANGE_MAPY_FLAG;
    Ipp32u RANGE_MAPUV_FLAG;
#endif
}VC1SequenceLayerHeader;

typedef struct
{
    Ipp8u  k_x;
    Ipp8u  k_y;
    Ipp16u r_x;
    Ipp16u r_y;
}VC1MVRange;

typedef struct
{
    Ipp16u   scaleopp;
    Ipp16u  scalesame1;
    Ipp16u   scalesame2;
    Ipp16u   scalezone1_x;
    Ipp16u   scalezone1_y;
    Ipp16u   zone1offset_x;
    Ipp16u   zone1offset_y;
}VC1PredictScaleValuesPPic;

typedef struct
{
    Ipp16u   scalesame;
    Ipp16u   scaleopp1;
    Ipp16u   scaleopp2;
    Ipp16u   scalezone1_x;
    Ipp16u   scalezone1_y;
    Ipp16u   zone1offset_x;
    Ipp16u   zone1offset_y;
}VC1PredictScaleValuesBPic;