📄 umc_dv_enc_segment_writer.h
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/*
// INTEL CORPORATION PROPRIETARY INFORMATION
// This software is supplied under the terms of a license agreement or
// nondisclosure agreement with Intel Corporation and may not be copied
// or disclosed except in accordance with the terms of that agreement.
// Copyright (c) 2006-2007 Intel Corporation. All Rights Reserved.
//
*/
#include "umc_defs.h"
#if defined (UMC_ENABLE_DV_VIDEO_ENCODER)
#ifndef __DV_SEGMENT_WRITER_H
#define __DV_SEGMENT_WRITER_H
#include "ippdefs.h"
#include "umc_structures.h"
namespace UMC
{
//This enumeration type corresponds to the Table 2 shown on the P.6 of the SMPTE 314M-2005
enum SectionType
{
Header = 0,
Subcode = 1,
VAUX = 2,
Audio = 3,
Video = -4,
Reserved0 = -3,
Reserved1 = -2,
Reserved2 = -1
};
// This structure corresponds to the Table 1 shown on the P.5 of the SMPTE 314M-2005
struct DIFBlockIDData
{
Ipp32s Arb : 4;
Ipp32u Res1 : 1;
SectionType SCT : 3;
Ipp32s Res2 : 2;
Ipp32u FSP : 1;
Ipp32u FSC : 1;
Ipp32s Dseq : 4;
Ipp32s DBN : 8;
};
// This structure corresponds to the Table 6 shown on the P.8 of the SMPTE 314M-2005
struct HeaderDIFBlockData
{
Ipp32s Res1 : 6;
Ipp32u zero : 1;
Ipp32u DSF : 1;
Ipp32s APT : 3;
Ipp32s Res2 : 5;
Ipp32s AP1 : 3;
Ipp32s Res3 : 4;
Ipp32u TF1 : 1;
Ipp32s AP2 : 3;
Ipp32s Res4 : 4;
Ipp32u TF2 : 1;
Ipp32s AP3 : 3;
Ipp32s Res5 : 4;
Ipp32u TF3 : 1;
};
class VideoEncoderParams;
class DVSegmentWriter
{
public:
DVSegmentWriter(void);
~DVSegmentWriter(void);
Status InitWriter(Ipp8s DSF, Ipp8u AppType);
void SetDVSegment(struct DV_SEGMENT **lpDVSegment);
void ReleaseWriter();
void StartDIFSequence(Ipp8u DIFSeqNum, Ipp8u FSC, Ipp8u FSP=1);
Ipp8u *m_pDest; // Destination pointer
protected:
void WriteIDSection(DIFBlockIDData *pIDData, SectionType SCT, Ipp8u DIFBlockNum);
void WriteHeader();
void WriteEmptyAudioSection();
Ipp8u m_VideoDataDIFBlockNum;
Ipp8u m_AudioDataDIFBlockNum;
Ipp8s m_DSF; //DIF Sequence flag:
//DSF = 0 for 525/60 system (10 DIF sequences included in a channel)
//DSF = 1 for 625/50 system (12 DIF sequences included in a channel)
Ipp8s m_DIFSeqNum;//(0..9 for 525/60 system, 0..11 for 625/50 system)
Ipp8s m_FSC; //0 - First, 1 - Second channel
Ipp8s m_FSP; //This bit is used in DV100 together with FSC to indicate channel number:
//(FSC, FSP): (0,1) - first channel; (1,1) - second; (0,0) third; (1,0)-fourth
Ipp8u m_AppType; //Application type: 0 means consumer digital VCR, 0x7 (111b) means that source is uknown
//This field is also used to distinguish DVSD (if 0) and DV25 (if 0x7)
};
}//namespace UMC
#endif //__DV_SEGMENT_WRITER_H
#endif //(UMC_ENABLE_DV_VIDEO_ENCODER)
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