📄 umc_vc1_dec_blk_adv.cpp
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/* /////////////////////////////////////////////////////////////////////////////
//
// INTEL CORPORATION PROPRIETARY INFORMATION
// This software is supplied under the terms of a license agreement or
// nondisclosure agreement with Intel Corporation and may not be copied
// or disclosed except in accordance with the terms of that agreement.
// Copyright(c) 2004-2007 Intel Corporation. All Rights Reserved.
//
//
// VC-1 (VC1) decoder, block layer advanced profile
//
*/
#include "umc_defs.h"
#if defined (UMC_ENABLE_VC1_VIDEO_DECODER)
#include "ippi.h"
#include "umc_vc1_dec_seq.h"
#include "umc_vc1_common_zigzag_tbl.h"
#include "umc_vc1_common_blk_order_tbl.h"
#include "umc_vc1_dec_run_level_tbl.h"
#include "umc_vc1_dec_debug.h"
#include "umc_vc1_dec_time_statistics.h"
#include "umc_vc1_dec_exception.h"
using namespace UMC::VC1Exceptions;
typedef Ipp8u (*DCPrediction)(VC1DCBlkParam* CurrBlk, VC1DCPredictors* PredData,
Ipp32s blk_num, Ipp16s* pBlock, Ipp32u FCM);
//static IppiSize QuantSize[4] = {VC1_PIXEL_IN_BLOCK, VC1_PIXEL_IN_BLOCK,
// VC1_PIXEL_IN_BLOCK/2, VC1_PIXEL_IN_BLOCK,
// VC1_PIXEL_IN_BLOCK, VC1_PIXEL_IN_BLOCK/2,
// VC1_PIXEL_IN_BLOCK/2, VC1_PIXEL_IN_BLOCK/2};
typedef IppStatus (*Reconstruct)(Ipp16s* pSrcDst,
Ipp32s srcDstStep,
Ipp32s doubleQuant,
Ipp32u BlkType);
static Reconstruct Reconstruct_table[] = {
_own_ippiReconstructInterUniform_VC1_16s_C1IR,
_own_ippiReconstructInterNonuniform_VC1_16s_C1IR
};
IppStatus _own_ippiReconstructIntraUniform_VC1_16s_C1IR (Ipp16s* pSrcDst, Ipp32s srcDstStep, Ipp32s doubleQuant)
{
IppiSize DstSizeNZ;
_own_ippiQuantInvIntraUniform_VC1_16s_C1IR(pSrcDst,
srcDstStep,
doubleQuant,
&DstSizeNZ);
//transformation
ippiTransform8x8Inv_VC1_16s_C1IR(pSrcDst,
srcDstStep,
DstSizeNZ);
return ippStsNoErr;
}
IppStatus _own_ippiReconstructIntraNonuniform_VC1_16s_C1IR (Ipp16s* pSrcDst, Ipp32s srcDstStep, Ipp32s doubleQuant)
{
IppiSize DstSizeNZ;
_own_ippiQuantInvIntraNonuniform_VC1_16s_C1IR(pSrcDst,
srcDstStep,
doubleQuant,
&DstSizeNZ);
//transformation
ippiTransform8x8Inv_VC1_16s_C1IR(pSrcDst,
srcDstStep,
DstSizeNZ);
return ippStsNoErr;
}
// Ipp32u BlkType - VC1_BLK_INTER8X8 = 0x1,
// VC1_BLK_INTER8X4 = 0x2,
// VC1_BLK_INTER4X8 = 0x4,
// VC1_BLK_INTER4X4 = 0x8,
IppStatus _own_ippiReconstructInterUniform_VC1_16s_C1IR (Ipp16s* pSrcDst, Ipp32s srcDstStep, Ipp32s doubleQuant,Ipp32u BlkType)
{
IppiSize DstSizeNZ[4];
static IppiSize QuantSize[4] = {VC1_PIXEL_IN_BLOCK, VC1_PIXEL_IN_BLOCK,
VC1_PIXEL_IN_BLOCK/2, VC1_PIXEL_IN_BLOCK,
VC1_PIXEL_IN_BLOCK, VC1_PIXEL_IN_BLOCK/2,
VC1_PIXEL_IN_BLOCK/2, VC1_PIXEL_IN_BLOCK/2};
//quantization and transformation
if (VC1_BLK_INTER8X8 == BlkType)
{
_own_ippiQuantInvInterUniform_VC1_16s_C1IR(pSrcDst,
srcDstStep,
doubleQuant,
QuantSize[0],
&DstSizeNZ[0]);
ippiTransform8x8Inv_VC1_16s_C1IR(pSrcDst,
srcDstStep,
DstSizeNZ[0]);
}
else if(VC1_BLK_INTER4X8 == BlkType)
{
_own_ippiQuantInvInterUniform_VC1_16s_C1IR(pSrcDst,
srcDstStep,
doubleQuant,
QuantSize[1],
&DstSizeNZ[0]);
_own_ippiQuantInvInterUniform_VC1_16s_C1IR(pSrcDst+4,
srcDstStep,
doubleQuant,
QuantSize[1],
&DstSizeNZ[1]);
ippiTransform4x8Inv_VC1_16s_C1IR(pSrcDst,
srcDstStep,
DstSizeNZ[0]);
ippiTransform4x8Inv_VC1_16s_C1IR(pSrcDst+4,
srcDstStep,
DstSizeNZ[1]);
}
else if(VC1_BLK_INTER8X4 == BlkType)
{
_own_ippiQuantInvInterUniform_VC1_16s_C1IR(pSrcDst,
srcDstStep,
doubleQuant,
QuantSize[2],
&DstSizeNZ[0]);
_own_ippiQuantInvInterUniform_VC1_16s_C1IR(pSrcDst + (srcDstStep << 1),
srcDstStep,
doubleQuant,
QuantSize[2],
&DstSizeNZ[1]);
ippiTransform8x4Inv_VC1_16s_C1IR(pSrcDst,
srcDstStep,
DstSizeNZ[0]);
ippiTransform8x4Inv_VC1_16s_C1IR(pSrcDst + (srcDstStep << 1),
srcDstStep,
DstSizeNZ[1]);
}
else if(VC1_BLK_INTER4X4 == BlkType)
{
_own_ippiQuantInvInterUniform_VC1_16s_C1IR(pSrcDst,
srcDstStep,
doubleQuant,
QuantSize[3],
&DstSizeNZ[0]);
_own_ippiQuantInvInterUniform_VC1_16s_C1IR(pSrcDst + 4,
srcDstStep,
doubleQuant,
QuantSize[3],
&DstSizeNZ[1]);
_own_ippiQuantInvInterUniform_VC1_16s_C1IR(pSrcDst + (srcDstStep << 1),
srcDstStep,
doubleQuant,
QuantSize[3],
&DstSizeNZ[2]);
_own_ippiQuantInvInterUniform_VC1_16s_C1IR(pSrcDst + 4 + (srcDstStep << 1),
srcDstStep,
doubleQuant,
QuantSize[3],
&DstSizeNZ[3]);
ippiTransform4x4Inv_VC1_16s_C1IR(pSrcDst,
srcDstStep,
DstSizeNZ[0]);
ippiTransform4x4Inv_VC1_16s_C1IR(pSrcDst+ 4,
srcDstStep,
DstSizeNZ[1]);
ippiTransform4x4Inv_VC1_16s_C1IR(pSrcDst + (srcDstStep<<1),
srcDstStep,
DstSizeNZ[2]);
ippiTransform4x4Inv_VC1_16s_C1IR(pSrcDst + (srcDstStep<<1) + 4,
srcDstStep,
DstSizeNZ[3]);
}
return ippStsNoErr;
}
IppStatus _own_ippiReconstructInterNonuniform_VC1_16s_C1IR (Ipp16s* pSrcDst, Ipp32s srcDstStep, Ipp32s doubleQuant,Ipp32u BlkType)
{
IppiSize DstSizeNZ[4];
static IppiSize QuantSize[4] = {VC1_PIXEL_IN_BLOCK, VC1_PIXEL_IN_BLOCK,
VC1_PIXEL_IN_BLOCK/2, VC1_PIXEL_IN_BLOCK,
VC1_PIXEL_IN_BLOCK, VC1_PIXEL_IN_BLOCK/2,
VC1_PIXEL_IN_BLOCK/2, VC1_PIXEL_IN_BLOCK/2};
//quantization and transformation
if (VC1_BLK_INTER8X8 == BlkType)
{
_own_ippiQuantInvInterNonuniform_VC1_16s_C1IR(pSrcDst,
srcDstStep,
doubleQuant,
QuantSize[0],
&DstSizeNZ[0]);
ippiTransform8x8Inv_VC1_16s_C1IR(pSrcDst,
srcDstStep,
DstSizeNZ[0]);
}
else if(VC1_BLK_INTER4X8 == BlkType)
{
_own_ippiQuantInvInterNonuniform_VC1_16s_C1IR(pSrcDst,
srcDstStep,
doubleQuant,
QuantSize[1],
&DstSizeNZ[0]);
_own_ippiQuantInvInterNonuniform_VC1_16s_C1IR(pSrcDst+4,
srcDstStep,
doubleQuant,
QuantSize[1],
&DstSizeNZ[1]);
ippiTransform4x8Inv_VC1_16s_C1IR(pSrcDst,
srcDstStep,
DstSizeNZ[0]);
ippiTransform4x8Inv_VC1_16s_C1IR(pSrcDst+4,
srcDstStep,
DstSizeNZ[1]);
}
else if(VC1_BLK_INTER8X4 == BlkType)
{
_own_ippiQuantInvInterNonuniform_VC1_16s_C1IR(pSrcDst,
srcDstStep,
doubleQuant,
QuantSize[2],
&DstSizeNZ[0]);
_own_ippiQuantInvInterNonuniform_VC1_16s_C1IR(pSrcDst + (srcDstStep << 1),
srcDstStep,
doubleQuant,
QuantSize[2],
&DstSizeNZ[1]);
ippiTransform8x4Inv_VC1_16s_C1IR(pSrcDst,
srcDstStep,
DstSizeNZ[0]);
ippiTransform8x4Inv_VC1_16s_C1IR(pSrcDst + (srcDstStep << 1),
srcDstStep,
DstSizeNZ[1]);
}
else if(VC1_BLK_INTER4X4 == BlkType)
{
_own_ippiQuantInvInterNonuniform_VC1_16s_C1IR(pSrcDst,
srcDstStep,
doubleQuant,
QuantSize[3],
&DstSizeNZ[0]);
_own_ippiQuantInvInterNonuniform_VC1_16s_C1IR(pSrcDst + 4,
srcDstStep,
doubleQuant,
QuantSize[3],
&DstSizeNZ[1]);
_own_ippiQuantInvInterNonuniform_VC1_16s_C1IR(pSrcDst + (srcDstStep << 1),
srcDstStep,
doubleQuant,
QuantSize[3],
&DstSizeNZ[2]);
_own_ippiQuantInvInterNonuniform_VC1_16s_C1IR(pSrcDst + 4 + (srcDstStep << 1),
srcDstStep,
doubleQuant,
QuantSize[3],
&DstSizeNZ[3]);
ippiTransform4x4Inv_VC1_16s_C1IR(pSrcDst,
srcDstStep,
DstSizeNZ[0]);
ippiTransform4x4Inv_VC1_16s_C1IR(pSrcDst+ 4,
srcDstStep,
DstSizeNZ[1]);
ippiTransform4x4Inv_VC1_16s_C1IR(pSrcDst + (srcDstStep<<1),
srcDstStep,
DstSizeNZ[2]);
ippiTransform4x4Inv_VC1_16s_C1IR(pSrcDst + (srcDstStep<<1) + 4,
srcDstStep,
DstSizeNZ[3]);
}
return ippStsNoErr;
}
inline static void PredictACLeft(Ipp16s* pCurrAC, Ipp32u CurrQuant,
Ipp16s* pPredAC, Ipp32u PredQuant,
Ipp32s Step)
{
Ipp32s i;
Ipp32s Scale = VC1_DQScaleTbl[CurrQuant-1] * (PredQuant-1);
Ipp32u step = Step;
for (i = 1; i<VC1_PIXEL_IN_BLOCK; i++, step+=Step)
pCurrAC[step] = pCurrAC[step] + (Ipp16s)((pPredAC[i] * Scale + 0x20000)>>18);
}
inline static void PredictACTop(Ipp16s* pCurrAC, Ipp32u CurrQuant,
Ipp16s* pPredAC, Ipp32u PredQuant)
{
Ipp32s i;
Ipp32s Scale = VC1_DQScaleTbl[CurrQuant-1] * (PredQuant-1);
for (i = 1; i<VC1_PIXEL_IN_BLOCK; i++)
pCurrAC[i] = pCurrAC[i] + (Ipp16s)((pPredAC[i] * Scale + 0x20000)>>18);
}
static Ipp8u GetDCACPrediction(VC1DCBlkParam* CurrBlk, VC1DCPredictors* PredData,
Ipp32s blk_num, Ipp16s* pBlock, Ipp32u FCM)
{
Ipp8u blkType = VC1_BLK_INTRA;
VC1DCPredictors DCPred;
Ipp8u PredPattern;
Ipp32u CurrQuant = PredData->DoubleQuant[2];
Ipp16s DCA, DCB, DCC, DC = 0;
Ipp32u step = VC1_pixel_table[blk_num];
memcpy(&DCPred, PredData, sizeof(VC1DCPredictors));
PredPattern = DCPred.BlkPattern[blk_num];
switch(PredPattern)
{
case 7:
{
DCA = DCPred.DC[VC1_PredDCIndex[0][blk_num]];
DCB = DCPred.DC[VC1_PredDCIndex[1][blk_num]];
DCC = DCPred.DC[VC1_PredDCIndex[2][blk_num]];
if (vc1_abs_16s(DCB - DCA) <= vc1_abs_16s(DCB - DCC))
{
#ifdef VC1_DEBUG_ON
VM_Debug::GetInstance(VC1DebugRoutine).vm_debug_frame(-1,VC1_COEFFS,
"DC left prediction\n");
#endif
DC = CurrBlk->DC + DCC;
PredictACLeft(pBlock, CurrQuant, DCPred.ACLEFT[VC1_PredDCIndex[2][blk_num]],
DCPred.DoubleQuant[VC1_QuantIndex[1][blk_num]], step);
blkType = VC1_BLK_INTRA_LEFT;
}
else
{
#ifdef VC1_DEBUG_ON
VM_Debug::GetInstance(VC1DebugRoutine).vm_debug_frame(-1,VC1_COEFFS,
"DC top prediction\n");
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