via-rhine.c

grub4dos-0.4.4-2008- 08-src.zip

/* rhine.c:Fast Ethernet driver for Linux. */
/*
	Adapted 09-jan-2000 by Paolo Marini ([e-mail])

        originally written by Donald Becker.

	This software may be used and distributed according to the terms
	of the GNU Public License (GPL), incorporated herein by reference.
	Drivers derived from this code also fall under the GPL and must retain
	this authorship and copyright notice.

	Under no circumstances are the authors responsible for
	the proper functioning of this software, nor do the authors assume any
	responsibility for damages incurred with its use.

	This driver is designed for the VIA VT86C100A Rhine-II PCI Fast Ethernet
	controller.

*/

static const char *version = "rhine.c v1.0.0 2000-01-07\n";

/* A few user-configurable values. */

/* Size of the in-memory receive ring. */
#define RX_BUF_LEN_IDX	3	/* 0==8K, 1==16K, 2==32K, 3==64K */
#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
#define TX_BUF_SIZE	1536
#define RX_BUF_SIZE	1536

/* PCI Tuning Parameters
   Threshold is bytes transferred to chip before transmission starts. */
#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024. */
#define RX_FIFO_THRESH	4	/* Rx buffer level before first PCI xfer.  */
#define RX_DMA_BURST	4	/* Maximum PCI burst, '4' is 256 bytes */
#define TX_DMA_BURST	4

/* Operational parameters that usually are not changed. */
/* Time in jiffies before concluding the transmitter is hung. */
#define TX_TIMEOUT  ((2000*HZ)/1000)

#include "etherboot.h"
#include "nic.h"
#include "pci.h"
#include "cards.h"

/* define all ioaddr */

#define byPAR0				ioaddr
#define byRCR				ioaddr + 6
#define byTCR				ioaddr + 7
#define byCR0				ioaddr + 8
#define byCR1				ioaddr + 9
#define byISR0				ioaddr + 0x0c
#define byISR1				ioaddr + 0x0d
#define byIMR0				ioaddr + 0x0e
#define byIMR1				ioaddr + 0x0f
#define byMAR0				ioaddr + 0x10
#define byMAR1				ioaddr + 0x11
#define byMAR2				ioaddr + 0x12
#define byMAR3				ioaddr + 0x13
#define byMAR4				ioaddr + 0x14
#define byMAR5				ioaddr + 0x15
#define byMAR6				ioaddr + 0x16
#define byMAR7				ioaddr + 0x17
#define dwCurrentRxDescAddr		ioaddr + 0x18
#define dwCurrentTxDescAddr		ioaddr + 0x1c
#define dwCurrentRDSE0			ioaddr + 0x20
#define dwCurrentRDSE1			ioaddr + 0x24
#define dwCurrentRDSE2			ioaddr + 0x28
#define dwCurrentRDSE3			ioaddr + 0x2c
#define dwNextRDSE0			ioaddr + 0x30
#define dwNextRDSE1			ioaddr + 0x34
#define dwNextRDSE2			ioaddr + 0x38
#define dwNextRDSE3			ioaddr + 0x3c
#define dwCurrentTDSE0			ioaddr + 0x40
#define dwCurrentTDSE1			ioaddr + 0x44
#define dwCurrentTDSE2			ioaddr + 0x48
#define dwCurrentTDSE3			ioaddr + 0x4c
#define dwNextTDSE0			ioaddr + 0x50
#define dwNextTDSE1			ioaddr + 0x54
#define dwNextTDSE2			ioaddr + 0x58
#define dwNextTDSE3			ioaddr + 0x5c
#define dwCurrRxDMAPtr			ioaddr + 0x60
#define dwCurrTxDMAPtr			ioaddr + 0x64
#define byMPHY				ioaddr + 0x6c
#define byMIISR				ioaddr + 0x6d
#define byBCR0				ioaddr + 0x6e
#define byBCR1				ioaddr + 0x6f
#define byMIICR				ioaddr + 0x70
#define byMIIAD				ioaddr + 0x71
#define wMIIDATA			ioaddr + 0x72
#define byEECSR				ioaddr + 0x74
#define byTEST				ioaddr + 0x75
#define byGPIO				ioaddr + 0x76
#define byCFGA				ioaddr + 0x78
#define byCFGB				ioaddr + 0x79
#define byCFGC				ioaddr + 0x7a
#define byCFGD				ioaddr + 0x7b
#define wTallyCntMPA			ioaddr + 0x7c
#define wTallyCntCRC			ioaddr + 0x7d
/*---------------------  Exioaddr Definitions -------------------------*/

/*
 * Bits in the RCR register
 */

#define RCR_RRFT2		0x80
#define RCR_RRFT1		0x40
#define RCR_RRFT0		0x20
#define RCR_PROM		0x10
#define RCR_AB			0x08
#define RCR_AM			0x04
#define RCR_AR			0x02
#define RCR_SEP			0x01

/*
 * Bits in the TCR register
 */

#define TCR_RTSF		0x80
#define TCR_RTFT1		0x40
#define TCR_RTFT0		0x20
#define TCR_OFSET		0x08
#define TCR_LB1			0x04	/* loopback[1] */
#define TCR_LB0			0x02	/* loopback[0] */

/*
 * Bits in the CR0 register
 */

#define CR0_RDMD		0x40	/* rx descriptor polling demand */
#define CR0_TDMD		0x20	/* tx descriptor polling demand */
#define CR0_TXON		0x10
#define CR0_RXON		0x08
#define CR0_STOP		0x04	/* stop NIC, default = 1 */
#define CR0_STRT		0x02	/* start NIC */
#define CR0_INIT		0x01	/* start init process */


/*
 * Bits in the CR1 register
 */

#define CR1_SFRST		0x80	/* software reset */
#define CR1_RDMD1		0x40	/* RDMD1 */
#define CR1_TDMD1		0x20	/* TDMD1 */
#define CR1_KEYPAG		0x10	/* turn on par/key */
#define CR1_DPOLL		0x08	/* disable rx/tx auto polling */
#define CR1_FDX			0x04	/* full duplex mode */
#define CR1_ETEN		0x02	/* early tx mode */
#define CR1_EREN		0x01	/* early rx mode */

/*
 * Bits in the CR register
 */

#define CR_RDMD			0x0040	/* rx descriptor polling demand */
#define CR_TDMD			0x0020	/* tx descriptor polling demand */
#define CR_TXON			0x0010
#define CR_RXON			0x0008
#define CR_STOP			0x0004	/* stop NIC, default = 1 */
#define CR_STRT			0x0002	/* start NIC */
#define CR_INIT			0x0001	/* start init process */
#define CR_SFRST		0x8000	/* software reset */
#define CR_RDMD1		0x4000	/* RDMD1 */
#define CR_TDMD1		0x2000	/* TDMD1 */
#define CR_KEYPAG		0x1000	/* turn on par/key */
#define CR_DPOLL		0x0800	/* disable rx/tx auto polling */
#define CR_FDX			0x0400	/* full duplex mode */
#define CR_ETEN			0x0200	/* early tx mode */
#define CR_EREN			0x0100	/* early rx mode */

/*
 * Bits in the IMR0 register
 */

#define IMR0_CNTM		0x80
#define IMR0_BEM		0x40
#define IMR0_RUM		0x20
#define IMR0_TUM		0x10
#define IMR0_TXEM		0x08
#define IMR0_RXEM		0x04
#define IMR0_PTXM		0x02
#define IMR0_PRXM		0x01

/* define imrshadow */

#define IMRShadow		0x5AFF

/*
 * Bits in the IMR1 register
 */

#define IMR1_INITM		0x80
#define IMR1_SRCM		0x40
#define IMR1_NBFM		0x10
#define IMR1_PRAIM		0x08
#define IMR1_RES0M		0x04
#define IMR1_ETM		0x02
#define IMR1_ERM		0x01

/*
 * Bits in the ISR register
 */

#define ISR_INITI		0x8000
#define ISR_SRCI		0x4000
#define ISR_ABTI		0x2000
#define ISR_NORBF		0x1000
#define ISR_PKTRA		0x0800
#define ISR_RES0		0x0400
#define ISR_ETI			0x0200
#define ISR_ERI			0x0100
#define ISR_CNT			0x0080
#define ISR_BE			0x0040
#define ISR_RU			0x0020
#define ISR_TU			0x0010
#define ISR_TXE			0x0008
#define ISR_RXE			0x0004
#define ISR_PTX			0x0002
#define ISR_PRX			0x0001

/*
 * Bits in the ISR0 register
 */

#define ISR0_CNT		0x80
#define ISR0_BE			0x40
#define ISR0_RU			0x20
#define ISR0_TU			0x10
#define ISR0_TXE		0x08
#define ISR0_RXE		0x04
#define ISR0_PTX		0x02
#define ISR0_PRX		0x01

/*
 * Bits in the ISR1 register
 */

#define ISR1_INITI		0x80
#define ISR1_SRCI		0x40
#define ISR1_NORBF		0x10
#define ISR1_PKTRA		0x08
#define ISR1_ETI		0x02
#define ISR1_ERI		0x01

/* ISR ABNORMAL CONDITION */

#define ISR_ABNORMAL ISR_BE+ISR_RU+ISR_TU+ISR_CNT+ISR_NORBF+ISR_PKTRA

/*
 * Bits in the MIISR register
 */

#define MIISR_MIIERR		0x08
#define MIISR_MRERR		0x04
#define MIISR_LNKFL		0x02
#define MIISR_SPEED		0x01

/*
 * Bits in the MIICR register
 */

#define MIICR_MAUTO		0x80
#define MIICR_RCMD		0x40
#define MIICR_WCMD		0x20
#define MIICR_MDPM		0x10
#define MIICR_MOUT		0x08
#define MIICR_MDO		0x04
#define MIICR_MDI		0x02
#define MIICR_MDC		0x01

/*
 * Bits in the EECSR register
 */

#define EECSR_EEPR		0x80	/* eeprom programed status, 73h means programed */
#define EECSR_EMBP		0x40	/* eeprom embeded programming */
#define EECSR_AUTOLD		0x20	/* eeprom content reload */
#define EECSR_DPM		0x10	/* eeprom direct programming */
#define EECSR_CS		0x08	/* eeprom CS pin */
#define EECSR_SK		0x04	/* eeprom SK pin */
#define EECSR_DI		0x02	/* eeprom DI pin */
#define EECSR_DO		0x01	/* eeprom DO pin */

/*
 * Bits in the BCR0 register
 */

#define BCR0_CRFT2		0x20
#define BCR0_CRFT1		0x10
#define BCR0_CRFT0		0x08
#define BCR0_DMAL2		0x04
#define BCR0_DMAL1		0x02
#define BCR0_DMAL0		0x01

/*
 * Bits in the BCR1 register
 */

#define BCR1_CTSF		0x20
#define BCR1_CTFT1		0x10
#define BCR1_CTFT0		0x08
#define BCR1_POT2		0x04
#define BCR1_POT1		0x02
#define BCR1_POT0		0x01

/*
 * Bits in the CFGA register
 */

#define CFGA_EELOAD		0x80	/* enable eeprom embeded and direct programming */
#define CFGA_JUMPER		0x40
#define CFGA_MTGPIO		0x08
#define CFGA_T10EN		0x02
#define CFGA_AUTO		0x01

/*
 * Bits in the CFGB register
 */

#define CFGB_PD			0x80
#define CFGB_POLEN		0x02
#define CFGB_LNKEN		0x01

/*
 * Bits in the CFGC register
 */

#define CFGC_M10TIO		0x80
#define CFGC_M10POL		0x40
#define CFGC_PHY1		0x20
#define CFGC_PHY0		0x10
#define CFGC_BTSEL		0x08
#define CFGC_BPS2		0x04	/* bootrom select[2] */
#define CFGC_BPS1		0x02	/* bootrom select[1] */
#define CFGC_BPS0		0x01	/* bootrom select[0] */

/*
 * Bits in the CFGD register
 */

#define CFGD_GPIOEN		0x80
#define CFGD_DIAG		0x40
#define CFGD_MAGIC		0x10
#define CFGD_CFDX		0x04
#define CFGD_CEREN		0x02
#define CFGD_CETEN		0x01

/* Bits in RSR */
#define RSR_RERR		0x00000001
#define RSR_CRC			0x00000002
#define RSR_FAE			0x00000004
#define RSR_FOV			0x00000008
#define RSR_LONG		0x00000010
#define RSR_RUNT		0x00000020
#define RSR_SERR		0x00000040
#define RSR_BUFF		0x00000080
#define RSR_EDP			0x00000100
#define RSR_STP			0x00000200
#define RSR_CHN			0x00000400
#define RSR_PHY			0x00000800
#define RSR_BAR			0x00001000
#define RSR_MAR			0x00002000
#define RSR_RXOK		0x00008000
#define RSR_ABNORMAL		RSR_RERR+RSR_LONG+RSR_RUNT

/* Bits in TSR */
#define TSR_NCR0		0x00000001
#define TSR_NCR1		0x00000002
#define TSR_NCR2		0x00000004
#define TSR_NCR3		0x00000008
#define TSR_COLS		0x00000010
#define TSR_CDH			0x00000080
#define TSR_ABT			0x00000100
#define TSR_OWC			0x00000200
#define TSR_CRS			0x00000400
#define TSR_UDF			0x00000800
#define TSR_TBUFF		0x00001000
#define TSR_SERR		0x00002000
#define TSR_JAB			0x00004000
#define TSR_TERR		0x00008000
#define TSR_ABNORMAL		TSR_TERR+TSR_OWC+TSR_ABT+TSR_JAB+TSR_CRS
#define TSR_OWN_BIT		0x80000000

#define CB_DELAY_LOOP_WAIT	10	/* 10ms */
/* enabled mask value of irq */

#define W_IMR_MASK_VALUE	0x1BFF	/* initial value of IMR */