rominit.s

S3C2440的启动汇编代码

/* romInit.s - HITSAT ROM initialization module */

/*
DESCRIPTION
	The entry code for VxWorks images that start running from ROM
	Such as 'bootrom' and 'vxWorks_rom'.
	The entry point romInit() is the first code executed on power-up.
	
	romInit() performs the minimal setup needed to\
	 call the generic C routine romStart() with parameter BOOT_COLD.

romInit() 

	masks interrupts:
		processor
		interrupt controller

	sets the initial stack pointer:
		to STACK_ADRS which is defined in configAll.h .
		Other hardware and device initialisation is performed later in the sysHwInit routine in sysLib.c.

sysToMonitor()

	jumps to a location after the beginning of romInit,
	 (defined by ROM_WARM_ADRS) to perform a "warm boot".
	 This entry point allows a parameter to be passed to romStart().

The routines in this module don't use the "C" frame pointer %r11@ ! or
establish a stack frame.

*/

/*
 * Behaviours:
 *		Save boot type;
 *		Turn off the watchdog;
 *		Take a delay for cold boot;
 *		Set MMU Control Register;
 *		Disable interrupts;
 *		Set system clock;
 *		Initialize memory;
 *		r1 now contains memory size: store this in Memory_Size variable;
 *		Initialize stack pointer;
 *		jump to C entry point in ROM;
 */

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "regs.h"	
#include "config.h"
#include "arch/arm/mmuArmLib.h"

        .data
        .globl   VAR(copyright_wind_river)
        .long    VAR(copyright_wind_river)

/* internals */

	.globl	FUNC(romInit)		/* start of system code */
	.globl	VAR(sdata)		/* start of data */
        .globl  _sdata
	.globl	VAR(s3c2410xMemSize)	/* actual memory size */


/* externals */

	.extern	FUNC(romStart)	/* system initialization routine */

_sdata:
VAR_LABEL(sdata)
	.asciz	"start of data"
	.balign	4

/* variables */

	.data

VAR_LABEL(s3c2410xMemSize)
	.long	0

	.text
	.balign 4

/*******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

* INTERNAL
* sysToMonitor examines the ROM for the first instruction and the string
* "Copy" in the third word so if this changes, sysToMonitor must be updated.
*/

_ARM_FUNCTION(romInit)
_romInit:
/*added by ddd,2008-7-3 16:09 to add except enty*/


    
cold:
	mov	r0, #BOOT_COLD	/* fall through to warm boot entry */
warm:
	b	start

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 2004 Samsung"
	.ascii   "\nCopyright 2004 HITSAT, Inc."
	.balign 4

start:
/* Turn off the watchdog. */
	
	ldr	r1, =rWTCON_ADR		/* r0->WTCON */
	ldr	r2, =rWTCON_INIT_VALUE	/* r1 = WTCON's initValue */
	str	r2, [r1]		/* Turn off the watch-dog */

/* Take a delay for cold boot. */

	teqs	r0, #BOOT_COLD
	moveq	r1, #____BOOT_DELAY_VALUE
	movne	r1, #1

delay_loop:
	subs	r1, r1, #1
	bne	delay_loop

	/*
	 * Set processor and MMU to known state as follows (we may have not
	 * been entered from a reset). We must do this before setting the CPU
	 * mode as we must set PROG32/DATA32.
	 *
	 * MMU Control Register layout.
	 *
	 * bit
	 *  0 M 0 MMU disabled
	 *  1 A 0 Address alignment fault disabled, initially
	 *  2 C 0 Data cache disabled
	 *  3 W 0 Write Buffer disabled
	 *  4 P 1 PROG32
	 *  5 D 1 DATA32
	 *  6 L 1 Should Be One (Late abort on earlier CPUs)
	 *  7 B ? Endianness (1 => big)
	 *  8 S 0 System bit to zero } Modifies MMU protections, not really
	 *  9 R 1 ROM bit to one     } relevant until MMU switched on later.
	 * 10 F 0 Should Be Zero
	 * 11 Z 0 Should Be Zero (Branch prediction control on 810)
	 * 12 I 0 Instruction cache control
	 */

/* Setup MMU Control Register */

	mov	r1, #MMU_INIT_VALUE		/* Defined in mmuArmLib.h */

#if defined(INTEGRATOR_EARLY_I_CACHE_ENABLE)
	orr	r1, r1, #MMUCR_I_ENABLE		/* conditionally enable Icache*/
#endif

	mcr	p15, 0, r1, c1, c0, 0	/* Write to MMU CR */

	/*
	 * If MMU was on before this, then we'd better hope it was set
	 * up for flat translation or there will be problems. The next
	 * 2/3 instructions will be fetched "translated" (number depends
	 * on CPU).
	 *
	 * We would like to discard the contents of the Write-Buffer
	 * altogether, but there is no facility to do this. Failing that,
	 * we do not want any pending writes to happen at a later stage,
	 * so drain the Write-Buffer, i.e. force any pending writes to
	 * happen now.
	 */

	/* drain write-buffer */
	mov	r1, #0				/* data SBZ */
	mcr	p15, 0, r1, c7, c10, 4

	/* Flush (invalidate) both I and D caches */

	mcr	p15, 0, r1, c7, c7, 0	/* R1 = 0 from above, data SBZ*/

        /*
	 * Set Process ID Register to zero, this effectively disables
	 * the process ID remapping feature.
	 */

	mov	r1, #0
	mcr	p15, 0, r1, c13, c0, 0

/* Disable CPU interrupts and individual interrupts in the interrupt controller. */

	mrs	r1, cpsr
	bic	r1, r1, #MASK_MODE
	orr	r1, r1, #(MODE_SVC32 | IRQ_ENABLE_Bit | FIQ_ENABLE_Bit)
	msr	cpsr, r1


	ldr	r1, =0xffffffff
	ldr	r2, =rINTMSK_ADR		/* R2->interrupt mask registor of controller */
	str	r1, [r2]			/* disable all sources */
	ldr	r2, =rINTSUBMSK_ADR		/* R2->sub-interrupt mask registor of controller */
	str	r1, [r2]			/* disable all sub-sources */

	/*
	 * Jump to the normal (higher) ROM Position. After a reset, the
	 * ROM is mapped into memory from* location zero upwards as well
	 * as in its normal position at This code could be executing in
	 * the lower position. We wish to be executing the code, still
	 * in ROM, but in its normal (higher) position before we remap
	 * the machine so that the ROM is no longer dual-mapped from zero
	 * upwards, but so that RAM appears from 0 upwards.
	 */

	ldr	pc, L$_HiPosn
HiPosn:

	/*
	 * We are now executing in the normal (higher, still in ROM)
	 * position in the memory map.  Remap memory to post-reset state,
	 * so that the ROM is not now dual-mapped to zero upwards, but
	 * RAM is mapped from zero, instead.
	 */

	/* phoenix_remap */
	/*
	MOV	r1, #INTEGRATOR_HDR_REMAP
	MOV	r2, #INTEGRATOR_HDR_BASE
	STR	r1, [r2, #INTEGRATOR_HDR_CTRL_OFFSET]
	*/
	
	
/* Set system clock.*/
	
	/* set the MMU control register asynchronous mode. */

	mrc	p15, 0, r2, c1, c0, 0
	orr	r2, r2, #MMUCR_ASYNC
	mcr	p15, 0, r2, c1, c0, 0

	/* Set PLL lock time. */
	ldr	r2, =rLOCKTIME_ADR
	ldr	r1, =rLOCKTIME_INIT_VALUE
	str	r1, [r2]
	
	/* Set FCLK:HCLK:PCLK = 1:2:4 */
	ldr	r2, =rCLKDIVN_ADR
	ldr	r1, =rCLKDIVN_INIT_VALUE
	str	r1, [r2]
	
	/* Set FCLK = 200MHz by Fosc = 12MHz */
	ldr	r2, =rMPLLCON_ADR
	ldr	r1, =rMPLLCON_INIT_VALUE
	/* 	ldr	r1, =0x5c040 */
	str	r1, [r2]
	
	/* Set clock control register */
	ldr	r2, =rCLKCON_ADR
	ldr	r1, =rCLKCON_INIT_VALUE
	str	r1, [r2]
	
	/* Set clock slow register */
	ldr	r2, =rCLKSLOW_ADR
	ldr	r1, =rCLKSLOW_INIT_VALUE
	str	r1, [r2]

/* Initialize memory . */

	/* Set bus width for each bank, 0x22111110 */
	ldr	r2, =rBWSCON_ADR
	ldr	r1, =rBWSCON_INIT_VALUE
	str	r1, [r2]
	
	/* Set bank0 and bank3 for flash and cs8900, 0x00000700 */
	ldr	r2, =rBANKCON0_ADR
	ldr	r1, =rBANKCON0_INIT_VALUE
	str	r1, [r2]

	ldr	r2, =rBANKCON3_ADR
	ldr	r1, =rBANKCON3_INIT_VALUE
	str	r1, [r2]
	
	/* Set bank6 for SDRAM, 0x00018000 */
	ldr	r2, =rBANKCON6_ADR
	ldr	r1, =rBANKCON6_INIT_VALUE
	str	r1, [r2]
 /*added by ddd, set bank7 for sdram*/
  ldr	r2, =rBANKCON7_ADR
	ldr	r1, =rBANKCON7_INIT_VALUE
	str	r1, [r2]
 
	/* Set refresh for SDRAM, 0x00860459 */
	ldr	r2, =rREFRESH_ADR
	ldr	r1, =rREFRESH_INIT_VALUE
	str	r1, [r2]
	
	/* Set bank size for SDRAM, 0x000000b7 */
	ldr	r2, =rBANKSIZE_ADR
	ldr	r1, =rBANKSIZE_INIT_VALUE
	str	r1, [r2]
	
	/* Set bank mode, 0x00000030 */
	ldr	r2, =rMRSRB6_ADR
	ldr	r1, =rMRSRB6_INIT_VALUE
	str	r1, [r2]
	
	/*added by ddd, set bank7 mode*/
	ldr	r2, =rMRSRB7_ADR
	ldr	r1, =rMRSRB7_INIT_VALUE
	str	r1, [r2]
	
#ifdef BSP_DEBUG_SIM
	/* added by ddd, 2008-06-26 */
	/* initialized the port B */
	ldr r2, =rGPBCON
	ldr r1, =rGPBCON_INIT_VALUE
	str r1, [r2]
	
	ldr r2, =rGPBUP
	ldr r1, =rGPBUP_VALUE	
	str r1, [r2]
	
	/* led */

	ldr r2, =rGPBDAT
	ldr r1, =led23on
	str r1, [r2]


#endif
	
	
/* r1 now contains memory size: store this in Memory_Size variable */
	
	ldr	r1, =SZ_64M
	ldr	r3, L$_memSize
	str	r1, [r3]

	mov	r3, r1		/* Need to return size in both these registers*/
	
/* Initialize the stack pointer to just before where the uncompress code, 
 * copied from ROM to RAM, will run. */

	ldr	sp, L$_STACK_ADDR
	mov	fp, #0			/* zero frame pointer */

/* jump to C entry point in ROM: routine - entry point + ROM base */

#if	(ARM_THUMB)
	ldr	r12, L$_rStrtInRom
	orr	r12, r12, #1		/* force Thumb state */
	bx	r12
#else
	ldr	pc, L$_rStrtInRom
#endif	/* (ARM_THUMB) */

/*added by ddd,2008-7-3 16:09 to add except enty*/


_ARM_FUNCTION(romUndef)

     _romUndef:
     mov	r0, #BOOT_COLD
     
     
_ARM_FUNCTION(romSwi)

     _romSwi:
     mov	r0, #BOOT_COLD
_ARM_FUNCTION(romPrefetch)

     _romPrefetch:
     mov	r0, #BOOT_COLD
_ARM_FUNCTION(romDataAbort)

     _romDataAbort:
     mov	r0, #BOOT_COLD
_ARM_FUNCTION(romReserved)

     _romReserved:    
     mov	r0, #BOOT_COLD                


_ARM_FUNCTION(romIRQ)

     _romIRQ:

     sub sp, sp, #4

     stmfd sp!, {r0}

 

     ldr r0, L$_promIRQ

     ldr r0, [r0] 

     str r0, [sp, #4]

     ldmfd sp!, {r0, pc}
_ARM_FUNCTION(romFIQ)

     _romFIQ:     
    mov	r0, #BOOT_COLD 
     
/******************************************************************************/

/*
 * PC-relative-addressable pointers - LDR Rn,=sym is broken
 * note "_" after "$" to stop preprocessor performing substitution
 */

	.balign	4

L$_HiPosn:
#ifdef BSP_DEBUG_SIM1
	.long	RAM_HIGH_ADRS + HiPosn - FUNC(romInit)
#else
	.long	ROM_TEXT_ADRS + HiPosn - FUNC(romInit)
#endif

L$_rStrtInRom:
#ifdef BSP_DEBUG_SIM1
	.long	RAM_HIGH_ADRS + FUNC(romStart) - FUNC(romInit)
#else
	.long	ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)
#endif

L$_STACK_ADDR:
	.long	STACK_ADRS

L$_memSize:
	.long	VAR(s3c2410xMemSize)
/*added by ddd*/
L$_promIRQ:
.long     S3C_EXC_BASE + 20

/*________RESET_ADR:	b	cold	 reset................0x00000000 */
/*________UND_ADR:	nop		 unknown ins..........0x00000004 */
/*________SWI_ADR:	nop		 software.............0x00000008 */
/*________IABT_ADR:	nop		 instruction abort....0x0000000c */
/*________DABT_ADR:	nop		 data abort...........0x00000010 */
/*			nop		 reserved.............0x00000014 */
/*________IRQ_ADR:	nop		 IRQ..................0x00000018 */
/*________FIQ_ADR:	nop		 FIQ..................0x0000001c */