cs8900aend.c

cs8900的VxWorks驱动

			(int)1,			/* change length 1, bit0 */
			(int)1			/* Value is 1 for disable EINT9's pull-up. */
			);
	mask32_change_bsp(
			(int*)0x56000060,	/* GPFCON of s3c2410x */
			(int)2,			/* start bit0 */
			(int)2,			/* change length 2, bit0..1 */
			(int)2			/* Value is 2 for EINT9. */
			);
	return 0;
}

/*
 * cs8900a_pin_disable - Disable the pin for the interrupt of cs8900a.
 * 
 * RETURNS: status(int).
 */
int cs8900a_pin_disable(void)
{
	mask32_change_bsp(
			(int*)0x56000060,	/* GPGCON of s3c2410x */
			(int)2,			/* start bit2 */
			(int)2,			/* change length 2, bit2..3 */
			(int)0			/* Value is 0 for input. */
			);
	mask32_change_bsp(
			(int*)0x5600008c,	/* EXTINT1 of s3c2410x */
			(int)4,			/* start bit4 */
			(int)4,			/* change length 4, bit4..7 */
			(int)1			/* Value is 4, that high level triggered for EINT0. */
			);
	mask32_change_bsp(
			(int*)0x560000a4,	/* EINTMASK of s3c2410x */
			(int)9,			/* start bit9 */
			(int)1,			/* change length 1, bit9 */
			(int)1			/* Value is 1 for disable EINT9 */
			);
	return 0;
}

/*
 * cs_pp_r - reads a word from the PacketPage
 *
 * This routine reads a word from the PacketPage at the specified offset.
 *
 * RETURNS: a word in the offset
 */

USHORT cs_pp_r(END_DEVICE * pDrvCtrl, USHORT offset)
{
	volatile USHORT temp_ushort = 0;
	if(pDrvCtrl->in_memory_mode == TRUE)
	{
		/* in memory mode */
		temp_ushort = *((volatile USHORT *)((pDrvCtrl->mem_addr) + CS_CHIP_MEM_BASE + offset));
		return temp_ushort;
	}
	else
	{
		/* in io mode */
		*((volatile USHORT *)((pDrvCtrl->io_addr) + CS_CHIP_IO_BASE + CS_PORT_PKTPG_PTR)) = offset;
		temp_ushort = *((volatile USHORT *)((pDrvCtrl->io_addr) + CS_CHIP_IO_BASE + CS_PORT_PKTPG_DATA));
		return temp_ushort;
	}
}

/*
 * cs_pp_w - writes a value to the PacketPage
 *
 * This routine writes a value to the PacketPage at the specified offset.
 *
 * RETURNS: N/A
 */

void cs_pp_w(END_DEVICE * pDrvCtrl, USHORT offset, USHORT value)
{
	if(pDrvCtrl->in_memory_mode == TRUE)
	{
		/* in memory mode */
		*((volatile USHORT *)((pDrvCtrl->mem_addr) + CS_CHIP_MEM_BASE + offset)) = value;
	}
	else
	{
		/* in io mode */
		*((volatile USHORT *)((pDrvCtrl->io_addr) + CS_CHIP_IO_BASE + CS_PORT_PKTPG_PTR)) = offset;
		*((volatile USHORT *)((pDrvCtrl->io_addr) + CS_CHIP_IO_BASE + CS_PORT_PKTPG_DATA)) = value;
	}
	return;
}


/* add by phoenix */
STATUS mask32_change_bsp(int* dist32, int num, int len, int src)
{
	UINT32 tempUINT32;

	tempUINT32 = *dist32;

	if(len <= 0) return ERROR;
	if((num+len) > 32) return ERROR;

	tempUINT32 = ((tempUINT32&(~(((1<<len)-1)<<num)))|((src&((1<<len)-1))<<num));

	*dist32 = tempUINT32;

	return OK;
}

/* cs_chip_rx_frame_drop - delete some receive frame. */
void cs_chip_rx_frame_drop(END_DEVICE * pDrvCtrl, int num)
{
	while(num--)
	{
		cs_pp_w(pDrvCtrl,CS_PKTPG_RX_CFG,
			((cs_pp_r(pDrvCtrl,CS_PKTPG_RX_CFG)) | CS_RX_CFG_SKIP));
	}

	return;
}
/* cs_generate_interrupt - generate a software interrupt for test. */
void cs_chip_generate_interrupt(END_DEVICE* pDrvCtrl)
{
	cs_pp_w(pDrvCtrl,CS_PKTPG_BUF_CFG,
		((cs_pp_r(pDrvCtrl,CS_PKTPG_BUF_CFG)) | CS_BUF_CFG_SW_INT));
	return;
}
/* cs_get_rx_miss_num - get the miss number of receive frames. */
int cs_chip_get_rx_miss_num(END_DEVICE* pDrvCtrl)
{
	int temp_int;
	temp_int = cs_pp_r(pDrvCtrl,CS_PKTPG_RX_MISS);
	temp_int = (temp_int >> 6) & 0x03ff;
	return temp_int;
}
/* cs_get_tx_col_num - get the collision number of transmit frames. */
int cs_chip_get_tx_col_num(END_DEVICE* pDrvCtrl)
{
	int temp_int;
	temp_int = cs_pp_r(pDrvCtrl,CS_PKTPG_TX_COL);
	temp_int = (temp_int >> 6) & 0x03ff;
	return temp_int;
}
/* cs_chip_to_mem_mode - set the cs to memory mode. */
STATUS cs_chip_to_mem_mode(END_DEVICE* pDrvCtrl, int flag)
{
	pDrvCtrl->in_memory_mode = FALSE;
	if(flag)
	{
		cs_pp_w(pDrvCtrl, CS_PKTPG_BUS_CTL,
			cs_pp_r(pDrvCtrl, CS_PKTPG_BUS_CTL) | CS_BUS_CTL_MEM_MODE);

		pDrvCtrl->in_memory_mode = TRUE;
	}
	else
	{
		cs_pp_w(pDrvCtrl, CS_PKTPG_BUS_CTL,
			cs_pp_r(pDrvCtrl, CS_PKTPG_BUS_CTL) & (~CS_BUS_CTL_MEM_MODE));

		pDrvCtrl->in_memory_mode = FALSE;
	}

	return OK;
}

/* cs_chip_self_reset - cs chip reset by software command. */
STATUS cs_chip_self_reset(END_DEVICE* pDrvCtrl)
{
	const int reset_time = 5;
	int wait_count = 0;

	/* do reset. */
	cs_pp_w(pDrvCtrl, CS_PKTPG_SELF_CTL,
			cs_pp_r(pDrvCtrl, CS_PKTPG_SELF_CTL) | CS_SELF_CTL_RESET);

	/* wait for reset finish. */
	while(!(cs_pp_r(pDrvCtrl, CS_PKTPG_SELF_ST) & CS_SELF_ST_INIT_DONE))
	{
		taskDelay(reset_time);
		if((wait_count++) >= CS_MAXLOOP) 
		{
			      /*added by ddd*/
		#ifdef cs8900_debug
		   printf("CS_CHIP_SELF_RESET Error!\n");
			rGPBDAT1=led1on;
		#endif
			

			return ERROR;
		}
	}
      /*added by ddd*/
	#ifdef cs8900_debug
	   printf("CS_CHIP_SELF_RESET OK!\n");
	rGPBDAT1=led1234on;
	#endif
	return OK;
}

/* cs_chip_int_enable - interrupt enable for cs chip. */
STATUS cs_chip_int_enable(END_DEVICE *	pDrvCtrl)
{
	/* set the master interrupt enable bit in cs chip. 0x0116 = 0x8017*/
	cs_pp_w(pDrvCtrl,
		CS_PKTPG_BUS_CTL, (cs_pp_r(pDrvCtrl, CS_PKTPG_BUS_CTL)) | CS_BUS_CTL_INT_ENBL);

	return OK;
}

/* cs_chip_event_enable - interrupt enable for cs chip. */
STATUS cs_chip_event_enable(END_DEVICE * pDrvCtrl)
{
	/* enable > data, < data, CRC_err, and Rx_OK interrupt. 0x0102 = 0x7103*/
	cs_pp_w(pDrvCtrl,
		CS_PKTPG_RX_CFG, (cs_pp_r(pDrvCtrl, CS_PKTPG_RX_CFG)) | CS_RX_CFG_ALL_IE);

	/* enable all of the tx interrupt. 0x0106 = 0x8fc7*/
	/*modified by ddd, 08-7-11 15:49*/
	cs_pp_w(pDrvCtrl, CS_PKTPG_TX_CFG, CS_TX_CFG_ALL_IE|0x0007);
      /*cs_pp_w(pDrvCtrl, CS_PKTPG_TX_CFG, CS_TX_CFG_ALL_IE) */
	/* enable Rx miss and Tx underrun interrupt. 0x010a = 0x070b*/
       /*modified by ddd, 08-7-11 15:53*/
	/*cs_pp_w(pDrvCtrl, CS_PKTPG_BUF_CFG,
		CS_BUF_CFG_RX_MISS_IE | CS_BUF_CFG_TX_UNDR_IE | CS_BUF_CFG_RDY4TX_IE);
       */
       cs_pp_w(pDrvCtrl, CS_PKTPG_BUF_CFG,
		CS_BUF_CFG_RX_MISS_IE | CS_BUF_CFG_TX_UNDR_IE | CS_BUF_CFG_RDY4TX_IE|0x000c);
	return OK;
}

/* cs_chip_int_disable - interrupt disable for cs chip. */
STATUS cs_chip_int_disable(END_DEVICE *	pDrvCtrl)
{
	/* clear the master interrupt enable bit in cs chip. */
	cs_pp_w(pDrvCtrl,
		CS_PKTPG_BUS_CTL, (cs_pp_r(pDrvCtrl, CS_PKTPG_BUS_CTL)) & (~CS_BUS_CTL_INT_ENBL));

	return OK;
}

/* cs_chip_event_disable - interrupt disable for cs chip. */
STATUS cs_chip_event_disable(END_DEVICE * pDrvCtrl)
{
	/* disable all of Rx interrupt. 0x0102 = ~0x7103*/
	cs_pp_w(pDrvCtrl,
		CS_PKTPG_RX_CFG, (cs_pp_r(pDrvCtrl, CS_PKTPG_RX_CFG)) & (~CS_RX_CFG_ALL_IE));

	/* disable all of Tx interrupt. 0x0106 = 0x0007*/
	cs_pp_w(pDrvCtrl, CS_PKTPG_TX_CFG, 0);

	/* disable buffer interrupt. 0x010a = 0x0013*/
	cs_pp_w(pDrvCtrl, CS_PKTPG_BUF_CFG, 0);

	return OK;
}
/* cs_chip_select_rx_frame_type - select the receiver frame type. */
STATUS cs_chip_select_rx_frame_type(END_DEVICE * pDrvCtrl,USHORT type_mask,int val)
{
	/* clear this bit. */
	if(val == 0)
	{
		cs_pp_w(pDrvCtrl,
			CS_PKTPG_RX_CTL, (cs_pp_r(pDrvCtrl, CS_PKTPG_RX_CTL)) & (~type_mask));

		return OK;
	}

	/* set this bit. */
	if(val == 1)
	{
		cs_pp_w(pDrvCtrl,
			CS_PKTPG_RX_CTL, (cs_pp_r(pDrvCtrl, CS_PKTPG_RX_CTL)) | type_mask);

		return OK;
	}

	return ERROR;
}

/* cs_chip_loop_set - on or off cs chip loop. */
STATUS cs_chip_loop_set(END_DEVICE * pDrvCtrl, int val)
{
	if(val == 1)
	{
		cs_chip_set_full_duplex(pDrvCtrl, 1);

		cs_pp_w(pDrvCtrl,
			CS_PKTPG_TEST_CTL, (cs_pp_r(pDrvCtrl, CS_PKTPG_TEST_CTL))
			| CS_TEST_CTL_ENDEC_LP | CS_TEST_CTL_FDX);

		return OK;
	}

	if(val == 0)
	{
		cs_pp_w(pDrvCtrl,
			CS_PKTPG_TEST_CTL, (cs_pp_r(pDrvCtrl, CS_PKTPG_TEST_CTL)) & (~CS_TEST_CTL_ENDEC_LP));

		return OK;
	}

	return ERROR;
}

/* cs_chip_set_full_duplex - set cs rx/tx mode to full duplex or half duplex. */
STATUS cs_chip_set_full_duplex(END_DEVICE * pDrvCtrl, int val)
{
	if(val == 1)
	{
		cs_pp_w(pDrvCtrl,
				CS_PKTPG_TEST_CTL, (cs_pp_r(pDrvCtrl, CS_PKTPG_TEST_CTL)) | CS_TEST_CTL_FDX);

		return OK;
	}

	if(val == 0)
	{
		cs_pp_w(pDrvCtrl,
				CS_PKTPG_TEST_CTL, (cs_pp_r(pDrvCtrl, CS_PKTPG_TEST_CTL)) & (~CS_TEST_CTL_FDX));

		return OK;
	}

	return ERROR;
}

/* cs_chip_set_link_dep - set cs run depend on link or independ. */
STATUS cs_chip_set_link_dep(END_DEVICE * pDrvCtrl, int val)
{
	if(val == 1)
	{
		cs_pp_w(pDrvCtrl,
				CS_PKTPG_TEST_CTL, (cs_pp_r(pDrvCtrl, CS_PKTPG_TEST_CTL)) | CS_TEST_CTL_DIS_LT);

		return OK;
	}

	if(val == 0)
	{
		cs_pp_w(pDrvCtrl,
				CS_PKTPG_TEST_CTL, (cs_pp_r(pDrvCtrl, CS_PKTPG_TEST_CTL)) & (~CS_TEST_CTL_DIS_LT));

		return OK;
	}

	return ERROR;
}

/* cs_chip_tx_force_terminate - force terminate tx frame for cs chip. */
STATUS cs_chip_tx_force_terminate(END_DEVICE * pDrvCtrl,int val)
{
	if(val == 1)
	{
		cs_pp_w(pDrvCtrl,
				CS_PKTPG_TX_CMD, (cs_pp_r(pDrvCtrl, CS_PKTPG_TX_CMD)) | CS_TX_CMD_FORCE);

		return OK;
	}

	if(val == 0)
	{
		cs_pp_w(pDrvCtrl,
				CS_PKTPG_TX_CMD, (cs_pp_r(pDrvCtrl, CS_PKTPG_TX_CMD)) & (~CS_TX_CMD_FORCE));

		return OK;
	}

	return ERROR;
}

/* cs_chip_set_tx_crc - on or off tx CRC. */
STATUS cs_chip_set_tx_crc(END_DEVICE * pDrvCtrl, int val)
{
	if(val == 0)
	{
		cs_pp_w(pDrvCtrl,
				CS_PKTPG_TX_CMD, (cs_pp_r(pDrvCtrl, CS_PKTPG_TX_CMD)) | CS_TX_CMD_NO_CRC);

		return OK;
	}

	if(val == 1)
	{
		cs_pp_w(pDrvCtrl,
				CS_PKTPG_TX_CMD, (cs_pp_r(pDrvCtrl, CS_PKTPG_TX_CMD)) & (~CS_TX_CMD_NO_CRC));

		return OK;
	}

	return ERROR;
}

/* cs_chip_send_frame - send one frame to cs chip. */
STATUS cs_chip_send_frame(END_DEVICE * pDrvCtrl, USHORT * p_src_buf, int length)
{
	USHORT	bus_status = 0;
	int	count = 0;
	int i;
	unsigned char * p_src_buffer = (unsigned char *)p_src_buf;

	if(length > 0)
	{

		  if(display_net_event) printf ("%s: %d\n", "Call cs_chip_send_framek, TX length is:", length);

		/* Request that the transmit be started after all data has been copied */
		*((USHORT *)(CS_CHIP_MEM_BASE + CS_PKTPG_TX_CMD)) = CS_TX_CMD_START_ALL;

		/* TODO - initiate device transmit. */
		*((USHORT *)(CS_CHIP_MEM_BASE + CS_PKTPG_TX_LENGTH)) = length;

		/* Read the busStatus register which indicates success of the request */
		bus_status = *((USHORT *)(CS_CHIP_MEM_BASE + CS_PKTPG_BUS_ST));

		if((!(bus_status & CS_BUS_ST_TX_BID_ERR)) && (bus_status & CS_BUS_ST_RDY4TXNOW))
		{
			/* The chip is ready for transmission now */
			/* Copy the frame to the chip to start transmission */
			for(count = 0; count < length; count+=2)
			{
				*((USHORT *)(CS_CHIP_MEM_BASE + CS_PKTPG_TX_FRAME + count)) = p_src_buf[count/2];
			}

			if(display_net_event) printf ("%s: %d\n", "TX ok, TX length is:", length);

			return OK;
		}
		else
		{
		     if (display_net_event)
		     	{
				if (bus_status & CS_BUS_ST_TX_BID_ERR)
					printf("Error, TX_BID_ERR!\n");
				else
					printf("Error, RDY4TXNOW error!\n");
					
			 }
			/* the chip tx buffer unuse. 
			if(display_net_event)printf("Error, the tx buffer is invalid!!!\n")*/;
			return ERROR;
		}
	}
	else
	{
		/* null frame. */
		if(display_net_event)printf("Error, the length of tx frame less 0!!!\n");
		return ERROR;
	}
}

/* cs_soft_end_init - initialize the END_DEVICE. */
STATUS cs_soft_end_init(END_DEVICE * pDrvCtrl)
{
	pDrvCtrl->chip_dma_num = CS_INIT_DMA_NUM;

	pDrvCtrl->chip_int_num = CS_INIT_INT_NUM;/*chip self interrupt, 0 for INTRQ0*/
	pDrvCtrl->ilevel = CS_EINT9_INT_NUM;

	/*modified by ddd, 08-7-11 16:51*/
	pDrvCtrl->ivec = CS_EINT9_INT_NUM; /*eint8~23 is 5 for s3c2440*/
	/*pDrvCtrl->ivec = CS_INIT_INT_NUM;*/

	pDrvCtrl->io_addr = CS_CHIP_IO_OFFSET;
	pDrvCtrl->mem_addr = CS_CHIP_MEM_OFFSET;

	pDrvCtrl->enetAddr[2] = (USHORT)0x313e;
	pDrvCtrl->enetAddr[1] = (USHORT)0xa5e6;
	pDrvCtrl->enetAddr[0] = (USHORT)0x0a00;

	pDrvCtrl->media_type = CS_MEDIA_10BASET;
	pDrvCtrl->in_memory_mode = FALSE;
	pDrvCtrl->resetting = FALSE;

	return OK;
}