dm9ks.c

DM9000A 网络芯片Linux下的驱动代码,买芯片才搞到的,很实用哦.

/*
  $Id: dm9ks.c,v 1.1.1.1 2004/12/02 10:02:45 jackal Exp $

  dm9ks.c: Version 1.10 12/29/2004
  
        A Davicom DM9000A/DM9010 ISA NIC fast Ethernet driver for Linux.
	Copyright (C) 1997 2004  Sten Wang Jackal Huang

	This program is free software; you can redistribute it and/or
	modify it under the terms of the GNU General Public License
	as published by the Free Software Foundation; either version 2
	of the License, or (at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
	GNU General Public License for more details.


  (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.

	
V1.00	10/13/2004	Add new function Early transmit & IP/TCP/UDP Checksum
			offload enable & flow control is default
V1.1	12/29/2004	Add Two packet mode & modify RX function
*/

#if defined(MODVERSIONS)
#include <linux/modversions.h>
#endif
				
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/version.h>
#include <asm/dma.h>
#include <linux/spinlock.h>
#include <linux/crc32.h>

/* Board/System/Debug information/definition ---------------- */

#define DM9KS_ID		0x90000A46

#define DM9KS_NCR		0x00	/* Network control Reg.*/
#define DM9KS_NSR		0x01	/* Network Status Reg.*/
#define DM9KS_TCR		0x02	/* TX control Reg.*/
#define DM9KS_RXCR		0x05	/* RX control Reg.*/
#define DM9KS_SMCR		0x2f 	/* Special Mode Control Reg.*/
#define DM9KS_ETCR		0x30	/* Early Transmit control/status Reg.*/
#define	DM9KS_TCCR		0x31	/* Checksum cntrol Reg. */
#define DM9KS_RCSR		0x32	/* Receive Checksum status Reg.*/
#define DM9KS_REG05		0x30	/* SKIP_CRC/SKIP_LONG */
#define DM9KS_REG08		0x37
#define DM9KS_REG09		0x38
#define DM9KS_REG0A		0x29	/* Flow Control Enable */ 
#define DM9KS_GPCR		0x1e	/* General purpose control register */
#define DM9KS_GPR		0x1f	/* General purpose register */
#define DM9KS_ISR		0xfe
#define DM9KS_IMR		0xff
#define DM9KS_REGFF		0x83	/* IMR */
#define DM9KS_DISINTR		0x80

#define DM9KS_PHY		0x40	/* PHY address 0x01 */
#define DM9KS_PKT_MAX		1536	/* Received packet max size */
#define DM9KS_PKT_RDY		0x01	/* Packet ready to receive */
#define DM9KS_MIN_IO		0x300
#define DM9KS_MAX_IO		0x370

#define DM9KS_VID_L		0x28
#define DM9KS_VID_H		0x29
#define DM9KS_PID_L		0x2A
#define DM9KS_PID_H		0x2B


#define DMFE_SUCC       	0
#define MAX_PACKET_SIZE 	1514
#define DMFE_MAX_MULTICAST 	14

#define DM9KS_RX_INTR		0x01
#define DM9KS_TX_INTR		0x02
#define DM9KS_OVERFLOW_INTR	0x04

#define DM9KS_DWORD_MODE	1
#define DM9KS_BYTE_MODE	2
#define DM9KS_WORD_MODE	0

#define TRUE			1
#define FALSE			0

#define MAXSIZE		16

#define DMFE_TIMER_WUT  jiffies+(HZ*2)	/* timer wakeup time : 2 second */
#define DMFE_TX_TIMEOUT (HZ*2)		/* tx packet time-out time 1.5 s" */
#if defined(AUTOMDIX)
#define DMFE_TIMER_MDIX	jiffies+(HZ*1)  /* timer wakeup time : 1 second */
#endif

#if defined(DM9KS_DEBUG)
#define DMFE_DBUG(dbug_now, msg, vaule)\
if (dmfe_debug||dbug_now) printk(KERN_ERR "dmfe: %s %x\n", msg, vaule)
#else
#define DMFE_DBUG(dbug_now, msg, vaule)\
if (dbug_now) printk(KERN_ERR "dmfe: %s %x\n", msg, vaule)
#endif

#if (IO_MODE == 1)
#define VALOUT(x, y)	outb(x, y)
#define VALIN(x)	inb(x)
typedef u8 DATA_TYPE;
#elif (IO_MODE == 2)
#define VALOUT(x, y)	outw(x, y)
#define VALIN(x)	inw(x)
typedef u16 DATA_TYPE;
#elif (IO_MODE == 4)
#define VALOUT(x, y)	outl(x, y)
#define VALIN(x)	inl(x)
typedef u32 DATA_TYPE;
#else
#error **** You should specify access mode ****
#endif 

#pragma pack(push, 1)
typedef struct _RX_DESC
{
	u8 rxbyte;
	u8 status;
	u16 length;
}RX_DESC;

typedef union{
	u8 buf[4];
	RX_DESC desc;
} rx_t;
#pragma pack(pop)

enum DM9KS_PHY_mode {
	DM9KS_10MHD   = 0, 
	DM9KS_100MHD  = 1, 
	DM9KS_10MFD   = 4,
	DM9KS_100MFD  = 5, 
	DM9KS_AUTO    = 8, 
};

/* Structure/enum declaration ------------------------------- */
typedef struct board_info {

	u32 runt_length_counter;	/* counter: RX length < 64byte */ 
	u32 long_length_counter;	/* counter: RX length > 1514byte */ 
	u32 reset_counter;		/* counter: RESET */ 
	u32 reset_tx_timeout;		/* RESET caused by TX Timeout */ 
	u32 reset_rx_status;		/* RESET caused by RX Statsus wrong */

	u16 io_addr;			/* Register I/O base address */
	u16 io_data;			/* Data I/O address */
	u16 irq;			/* IRQ */

	u16 tx_pkt_cnt;
	u16 sent_pkt_len, queue_pkt_len;
	u16 queue_start_addr;
	u16 dbug_cnt;

	u8 op_mode;			/* PHY operation mode */
	u8 io_mode;			/* 0:word, 2:byte */
	u8 phy_addr;
	u8 link_failed;			/* Ever link failed */
	u8 nsr;				/*Network Status Register */
	u8 link_status;			/* Detect link state */
	u8 device_wait_reset;		/* device state */
	u8 ncr;
	u8 flowcontrol_p;

	struct timer_list timer;
	struct net_device_stats stats;
	unsigned char srom[128];
	spinlock_t lock;

} board_info_t;

/* Global variable declaration ----------------------------- */
static int dmfe_debug = 0;
static struct net_device * dmfe_dev = NULL;

/* For module input parameter */
static int debug      = 0;
static int mode       = DM9KS_AUTO;
static int media_mode = DM9KS_AUTO;
static u8 irqline     = 3;

/* function declaration ------------------------------------- */
int dmfe_probe(struct net_device *);
static int dmfe_open(struct net_device *);
static int dmfe_start_xmit(struct sk_buff *, struct net_device *);
static void dmfe_tx_done(unsigned long);
static void dmfe_packet_receive(struct net_device *);
static int dmfe_stop(struct net_device *);
static struct net_device_stats * dmfe_get_stats(struct net_device *); 
static int dmfe_do_ioctl(struct net_device *, struct ifreq *, int);
static void dmfe_interrupt(int , void *, struct pt_regs *);
static void dmfe_timer(unsigned long);
static void dmfe_init_dm9000(struct net_device *);
static void dmfe_reset_dm9000(struct net_device *);
static unsigned long cal_CRC(unsigned char *, unsigned int, u8);
static u8 ior(board_info_t *, int);
static void iow(board_info_t *, int, u8);
static u16 phy_read(board_info_t *, int);
static void phy_write(board_info_t *, int, u16);
static u16 read_srom_word(board_info_t *, int);
static void dm9000_hash_table(struct net_device *);
#if defined(CHECKSUM)
static u8 check_rx_ready(u8);
#endif

DECLARE_TASKLET(dmfe_tx_tasklet,dmfe_tx_done,0);

/* DM9000 network baord routine ---------------------------- */

/*
  Search DM9000 board, allocate space and register it
*/
int dmfe_probe(struct net_device *dev)
{
	struct board_info *db;    /* Point a board information structure */
	u32 id_val;
	u16 iobase = DM9KS_MIN_IO;
	u16 i, dm9000_found = FALSE;

	DMFE_DBUG(0, "dmfe_probe()",0);


	/* Search All DM9000 serial NIC */
	do {
		outb(DM9KS_VID_L, iobase);
		id_val = inb(iobase + 4);
		outb(DM9KS_VID_H, iobase);
		id_val |= inb(iobase + 4) << 8;
		outb(DM9KS_PID_L, iobase);
		id_val |= inb(iobase + 4) << 16;
		outb(DM9KS_PID_H, iobase);
		id_val |= inb(iobase + 4) << 24;

		if (id_val == DM9KS_ID) {
			
			printk("<DM9KS> I/O: %x, VID: %x \n",iobase, id_val);
			dm9000_found = TRUE;

			/* Init network device */
			dev = init_etherdev(dev, 0);
			
			/* Allocated board information structure */
			db = (void *)(kmalloc(sizeof(*db), GFP_KERNEL));
			memset(db, 0, sizeof(*db));
			dev->priv   = db;   /* link device and board info */
			dmfe_dev    = dev;
			db->io_addr  = iobase;
			db->io_data = iobase + 4;

			/* driver system function */
			ether_setup(dev);
				
			dev->base_addr 		= iobase;
			dev->irq 		= irqline;
			dev->open 		= &dmfe_open;
			dev->hard_start_xmit 	= &dmfe_start_xmit;
			dev->stop 		= &dmfe_stop;
			dev->get_stats 		= &dmfe_get_stats;
			dev->set_multicast_list = &dm9000_hash_table;
			dev->do_ioctl 		= &dmfe_do_ioctl;

#if defined(CHECKSUM)
			(struct det_device*)dev->features = dev->features | NETIF_F_NO_CSUM;
#endif

			SET_MODULE_OWNER(dev);


			/* Read SROM content */
			for (i=0; i<64; i++)
				((u16 *)db->srom)[i] = read_srom_word(db, i);

			/* Set Node Address */
			for (i=0; i<6; i++)
				dev->dev_addr[i] = db->srom[i];

			/* Request IO from system */
			request_region(iobase, 2, dev->name);

		}
		iobase += 0x10;
	}while(!dm9000_found && iobase <= DM9KS_MAX_IO);

	return dm9000_found ? 0:-ENODEV;
}

/*
  Open the interface.
  The interface is opened whenever "ifconfig" actives it.
*/
static int dmfe_open(struct net_device *dev)
{
	board_info_t * db = (board_info_t *)dev->priv;
	DMFE_DBUG(0, "dmfe_open", 0);
	MOD_INC_USE_COUNT;

	if (request_irq(dev->irq,&dmfe_interrupt,SA_SHIRQ,dev->name,dev)) 
		return -EAGAIN;

	/* Initilize DM910X board */
	dmfe_init_dm9000(dev);
 
	/* Init driver variable */
	db->dbug_cnt 		= 0;
	db->runt_length_counter = 0;
	db->long_length_counter = 0;
	db->reset_counter 	= 0;

	/* set and active a timer process */
	init_timer(&db->timer);
	db->timer.expires 	= DMFE_TIMER_WUT * 2;
	db->timer.data 		= (unsigned long)dev;
	db->timer.function 	= &dmfe_timer;
	add_timer(&db->timer);	//Move to DM9000 initiallization was finished.
	
	netif_start_queue(dev);

	return 0;
}

/* Set PHY operationg mode
*/
static void set_PHY_mode(board_info_t *db)
{
	u16 phy_reg0 = 0x1200;		/* Auto-negotiation & duplux disable */
	u16 phy_reg4 = 0x01e1;		/* Default flow control disable*/

	if ( !(db->op_mode & DM9KS_AUTO) ) // op_mode didn't auto sense */
	{ 
		switch(db->op_mode) {
			case DM9KS_10MHD:  phy_reg4 = 0x21; 
                        	           phy_reg0 = 0x1000;
					   break;
			case DM9KS_10MFD:  phy_reg4 = 0x41; 
					   phy_reg0 = 0x1100;
                                	   break;
			case DM9KS_100MHD: phy_reg4 = 0x81; 
					   phy_reg0 = 0x3000;
				    	   break;
			case DM9KS_100MFD: phy_reg4 = 0x101; 
					   phy_reg0 = 0x3100;
				   	   break;
			default: 
					   break;
		} // end of switch
	
	} // end of if
	phy_write(db, 0, phy_reg0);
	phy_write(db, 4, phy_reg4);
}

/* 
	Initilize dm9000 board
*/
static void dmfe_init_dm9000(struct net_device *dev)
{
	board_info_t *db = (board_info_t *)dev->priv;
	DMFE_DBUG(0, "dmfe_init_dm9000()", 0);

	/* set the internal PHY power-on, GPIOs normal, and wait 2ms */
	iow(db, 0x1F, 0);	/* GPR (reg_1Fh)bit GPIO0=0 pre-activate PHY */
	udelay(20);		/* wait 2ms for PHY power-on ready */

	/* do a software reset and wait 20us */
	iow(db, DM9KS_NCR, 3);
	udelay(20);		/* wait 20us at least for software reset ok */
	iow(db, DM9KS_NCR, 3);	/* NCR (reg_00h) bit[0] RST=1 & Loopback=1, reset on. Added by SPenser */
	udelay(20);		/* wait 20us at least for software reset ok */

	/* I/O mode */
	db->io_mode = ior(db, DM9KS_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */

	/* Set PHY */
	db->op_mode = media_mode;
	set_PHY_mode(db);

	/* Program operating register */
	iow(db, DM9KS_NCR, 0);
	iow(db, DM9KS_TCR, 0);		/* TX Polling clear */
	iow(db, 0x08, 0x3f);		/* Less 3kb, 600us */
	iow(db, 0x2f, 0);		/* Special Mode */
	iow(db, DM9KS_NSR, 0x2c);	/* clear TX status */
	iow(db, DM9KS_ISR, 0x0f); 		/* Clear interrupt status */

	/* Added by jackal at 03/29/2004 */
#if defined(CHECKSUM)
	iow(db, DM9KS_ETCR, 0);		/* Early transmit disable */
	iow(db, DM9KS_TCCR, 0x07);	/* TX UDP/TCP/IP checksum enable */
	iow(db, DM9KS_RCSR, 0x03);	/*Receive checksum enable & discard checksum error packet */
#endif
 
	/* Set address filter table */
	dm9000_hash_table(dev);

	/* Activate DM9000A/DM9010 */
	iow(db, DM9KS_RXCR, DM9KS_REG05 | 1);	/* RX enable */
	iow(db, DM9KS_IMR, DM9KS_REGFF); 	// Enable TX/RX interrupt mask
 
	/* Init Driver variable */
	db->link_failed 	= 1;
	db->tx_pkt_cnt 		= 0;
	db->queue_pkt_len 	= 0;
	dev->trans_start 	= 0;

	db->flowcontrol_p = 1;
	
	netif_carrier_on(dev);
	spin_lock_init(&db->lock);

}

/* 
	Reset dm9000 board due to 32bits mode while excess collision or late collision.
*/

static void dmfe_reset_dm9000(struct net_device *dev)
{
	board_info_t *db = (board_info_t *)dev->priv;
	DMFE_DBUG(0, "dmfe_reset_dm9000()", 0);

	iow(db, 0, 1);		/* NCR (reg_00h) bit[0] RST=1, reset on. Added by SPenser */
	udelay(1);		/* wait 20us at least for software reset ok */
	iow(db, 0, 0);
	
	/* software reset 2 times */
	iow(db, DM9KS_NCR, 3);
	udelay(20);
	iow(db, DM9KS_NCR, 3);
	udelay(20);

	/* Program operating register */
	iow(db, DM9KS_NCR, 0);
	iow(db, DM9KS_TCR, 0);		/* TX Polling clear */
	iow(db, 0x08, 0x3f);		/* Less 3Kb, 600us */
	iow(db, 0x2f, 0);		/* Special Mode */
	iow(db, DM9KS_NSR, 0x2c);	/* clear TX status */
	iow(db, DM9KS_ISR, 0x0f); 		/* Clear interrupt status */

	/* Activate DM9000A/DM9010 */
	iow(db, DM9KS_RXCR, DM9KS_REG05 | 1);	/* RX enable */
	iow(db, DM9KS_IMR, DM9KS_REGFF);  	// Enable TX/RX interrupt mask
 
	/* Init Driver variable */
	db->link_failed 	= 1;
	db->tx_pkt_cnt 		= 0;
	db->queue_pkt_len 	= 0;
	dev->trans_start 	= 0;

	netif_carrier_on(dev);

} 

/*
  Hardware start transmission.
  Send a packet to media from the upper layer.
*/
static int dmfe_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
	board_info_t *db = (board_info_t *)dev->priv;
	DATA_TYPE * data_ptr;
	int i, tmplen;

	DMFE_DBUG(0, "dmfe_start_xmit", 0);

	if (db->tx_pkt_cnt >= 2)
		return 1;

	db->stats.tx_packets++;
	db->stats.tx_bytes+=skb->len;
	netif_stop_queue(dev);

	/* Disable all interrupt */
	iow(db, 0xff, DM9KS_DISINTR);

	/* Move data to TX SRAM */