rtc_reg.h

Atheros Communications AR6001 WLAN Driver for SDIO installation Read Me March 26,2007 (based on

#define CORE_CLOCK_REDUCED_GET(x)                (((x) & CORE_CLOCK_REDUCED_MASK) >> CORE_CLOCK_REDUCED_LSB)
#define CORE_CLOCK_REDUCED_SET(x)                (((x) << CORE_CLOCK_REDUCED_LSB) & CORE_CLOCK_REDUCED_MASK)

#define CPU_CLOCK_ADDRESS                        0x0c000024
#define CPU_CLOCK_OFFSET                         0x00000024
#define CPU_CLOCK_DISABLE_SYNC_MSB               12
#define CPU_CLOCK_DISABLE_SYNC_LSB               12
#define CPU_CLOCK_DISABLE_SYNC_MASK              0x00001000
#define CPU_CLOCK_DISABLE_SYNC_GET(x)            (((x) & CPU_CLOCK_DISABLE_SYNC_MASK) >> CPU_CLOCK_DISABLE_SYNC_LSB)
#define CPU_CLOCK_DISABLE_SYNC_SET(x)            (((x) << CPU_CLOCK_DISABLE_SYNC_LSB) & CPU_CLOCK_DISABLE_SYNC_MASK)
#define CPU_CLOCK_STANDARD_MSB                   9
#define CPU_CLOCK_STANDARD_LSB                   8
#define CPU_CLOCK_STANDARD_MASK                  0x00000300
#define CPU_CLOCK_STANDARD_GET(x)                (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB)
#define CPU_CLOCK_STANDARD_SET(x)                (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
#define CPU_CLOCK_REDUCED_MSB                    1
#define CPU_CLOCK_REDUCED_LSB                    0
#define CPU_CLOCK_REDUCED_MASK                   0x00000003
#define CPU_CLOCK_REDUCED_GET(x)                 (((x) & CPU_CLOCK_REDUCED_MASK) >> CPU_CLOCK_REDUCED_LSB)
#define CPU_CLOCK_REDUCED_SET(x)                 (((x) << CPU_CLOCK_REDUCED_LSB) & CPU_CLOCK_REDUCED_MASK)

#define CLOCK_OUT_ADDRESS                        0x0c000028
#define CLOCK_OUT_OFFSET                         0x00000028
#define CLOCK_OUT_SELECT_MSB                     3
#define CLOCK_OUT_SELECT_LSB                     0
#define CLOCK_OUT_SELECT_MASK                    0x0000000f
#define CLOCK_OUT_SELECT_GET(x)                  (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB)
#define CLOCK_OUT_SELECT_SET(x)                  (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK)

#define CLOCK_CONTROL_ADDRESS                    0x0c00002c
#define CLOCK_CONTROL_OFFSET                     0x0000002c
#define CLOCK_CONTROL_UART_CLK_MSB               1
#define CLOCK_CONTROL_UART_CLK_LSB               1
#define CLOCK_CONTROL_UART_CLK_MASK              0x00000002
#define CLOCK_CONTROL_UART_CLK_GET(x)            (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB)
#define CLOCK_CONTROL_UART_CLK_SET(x)            (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK)
#define CLOCK_CONTROL_SI0_CLK_MSB                0
#define CLOCK_CONTROL_SI0_CLK_LSB                0
#define CLOCK_CONTROL_SI0_CLK_MASK               0x00000001
#define CLOCK_CONTROL_SI0_CLK_GET(x)             (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB)
#define CLOCK_CONTROL_SI0_CLK_SET(x)             (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK)

#define BIAS_OVERRIDE_ADDRESS                    0x0c000030
#define BIAS_OVERRIDE_OFFSET                     0x00000030
#define BIAS_OVERRIDE_ON_MSB                     0
#define BIAS_OVERRIDE_ON_LSB                     0
#define BIAS_OVERRIDE_ON_MASK                    0x00000001
#define BIAS_OVERRIDE_ON_GET(x)                  (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB)
#define BIAS_OVERRIDE_ON_SET(x)                  (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK)

#define REF_VOLTAGE_TRIM_ADDRESS                 0x0c000034
#define REF_VOLTAGE_TRIM_OFFSET                  0x00000034
#define REF_VOLTAGE_TRIM_REFSEL_MSB              3
#define REF_VOLTAGE_TRIM_REFSEL_LSB              0
#define REF_VOLTAGE_TRIM_REFSEL_MASK             0x0000000f
#define REF_VOLTAGE_TRIM_REFSEL_GET(x)           (((x) & REF_VOLTAGE_TRIM_REFSEL_MASK) >> REF_VOLTAGE_TRIM_REFSEL_LSB)
#define REF_VOLTAGE_TRIM_REFSEL_SET(x)           (((x) << REF_VOLTAGE_TRIM_REFSEL_LSB) & REF_VOLTAGE_TRIM_REFSEL_MASK)

#define LDO_CONTROL_ADDRESS                      0x0c000038
#define LDO_CONTROL_OFFSET                       0x00000038
#define LDO_CONTROL_CORE_LIMIT_OFF_MSB           14
#define LDO_CONTROL_CORE_LIMIT_OFF_LSB           14
#define LDO_CONTROL_CORE_LIMIT_OFF_MASK          0x00004000
#define LDO_CONTROL_CORE_LIMIT_OFF_GET(x)        (((x) & LDO_CONTROL_CORE_LIMIT_OFF_MASK) >> LDO_CONTROL_CORE_LIMIT_OFF_LSB)
#define LDO_CONTROL_CORE_LIMIT_OFF_SET(x)        (((x) << LDO_CONTROL_CORE_LIMIT_OFF_LSB) & LDO_CONTROL_CORE_LIMIT_OFF_MASK)
#define LDO_CONTROL_CORE_LIMIT_MSB               13
#define LDO_CONTROL_CORE_LIMIT_LSB               11
#define LDO_CONTROL_CORE_LIMIT_MASK              0x00003800
#define LDO_CONTROL_CORE_LIMIT_GET(x)            (((x) & LDO_CONTROL_CORE_LIMIT_MASK) >> LDO_CONTROL_CORE_LIMIT_LSB)
#define LDO_CONTROL_CORE_LIMIT_SET(x)            (((x) << LDO_CONTROL_CORE_LIMIT_LSB) & LDO_CONTROL_CORE_LIMIT_MASK)
#define LDO_CONTROL_CORE_REG_Z_MSB               10
#define LDO_CONTROL_CORE_REG_Z_LSB               8
#define LDO_CONTROL_CORE_REG_Z_MASK              0x00000700
#define LDO_CONTROL_CORE_REG_Z_GET(x)            (((x) & LDO_CONTROL_CORE_REG_Z_MASK) >> LDO_CONTROL_CORE_REG_Z_LSB)
#define LDO_CONTROL_CORE_REG_Z_SET(x)            (((x) << LDO_CONTROL_CORE_REG_Z_LSB) & LDO_CONTROL_CORE_REG_Z_MASK)
#define LDO_CONTROL_RADIO_LIMIT_OFF_MSB          6
#define LDO_CONTROL_RADIO_LIMIT_OFF_LSB          6
#define LDO_CONTROL_RADIO_LIMIT_OFF_MASK         0x00000040
#define LDO_CONTROL_RADIO_LIMIT_OFF_GET(x)       (((x) & LDO_CONTROL_RADIO_LIMIT_OFF_MASK) >> LDO_CONTROL_RADIO_LIMIT_OFF_LSB)
#define LDO_CONTROL_RADIO_LIMIT_OFF_SET(x)       (((x) << LDO_CONTROL_RADIO_LIMIT_OFF_LSB) & LDO_CONTROL_RADIO_LIMIT_OFF_MASK)
#define LDO_CONTROL_RADIO_LIMIT_MSB              5
#define LDO_CONTROL_RADIO_LIMIT_LSB              3
#define LDO_CONTROL_RADIO_LIMIT_MASK             0x00000038
#define LDO_CONTROL_RADIO_LIMIT_GET(x)           (((x) & LDO_CONTROL_RADIO_LIMIT_MASK) >> LDO_CONTROL_RADIO_LIMIT_LSB)
#define LDO_CONTROL_RADIO_LIMIT_SET(x)           (((x) << LDO_CONTROL_RADIO_LIMIT_LSB) & LDO_CONTROL_RADIO_LIMIT_MASK)
#define LDO_CONTROL_RADIO_REG_Z_MSB              2
#define LDO_CONTROL_RADIO_REG_Z_LSB              0
#define LDO_CONTROL_RADIO_REG_Z_MASK             0x00000007
#define LDO_CONTROL_RADIO_REG_Z_GET(x)           (((x) & LDO_CONTROL_RADIO_REG_Z_MASK) >> LDO_CONTROL_RADIO_REG_Z_LSB)
#define LDO_CONTROL_RADIO_REG_Z_SET(x)           (((x) << LDO_CONTROL_RADIO_REG_Z_LSB) & LDO_CONTROL_RADIO_REG_Z_MASK)

#define WDT_CONTROL_ADDRESS                      0x0c00003c
#define WDT_CONTROL_OFFSET                       0x0000003c
#define WDT_CONTROL_ACTION_MSB                   2
#define WDT_CONTROL_ACTION_LSB                   0
#define WDT_CONTROL_ACTION_MASK                  0x00000007
#define WDT_CONTROL_ACTION_GET(x)                (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB)
#define WDT_CONTROL_ACTION_SET(x)                (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK)

#define WDT_STATUS_ADDRESS                       0x0c000040
#define WDT_STATUS_OFFSET                        0x00000040
#define WDT_STATUS_INTERRUPT_MSB                 0
#define WDT_STATUS_INTERRUPT_LSB                 0
#define WDT_STATUS_INTERRUPT_MASK                0x00000001
#define WDT_STATUS_INTERRUPT_GET(x)              (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB)
#define WDT_STATUS_INTERRUPT_SET(x)              (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK)

#define WDT_ADDRESS                              0x0c000044
#define WDT_OFFSET                               0x00000044
#define WDT_TARGET_MSB                           21
#define WDT_TARGET_LSB                           0
#define WDT_TARGET_MASK                          0x003fffff
#define WDT_TARGET_GET(x)                        (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB)
#define WDT_TARGET_SET(x)                        (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK)

#define WDT_COUNT_ADDRESS                        0x0c000048
#define WDT_COUNT_OFFSET                         0x00000048
#define WDT_COUNT_VALUE_MSB                      21
#define WDT_COUNT_VALUE_LSB                      0
#define WDT_COUNT_VALUE_MASK                     0x003fffff
#define WDT_COUNT_VALUE_GET(x)                   (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB)
#define WDT_COUNT_VALUE_SET(x)                   (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK)

#define WDT_RESET_ADDRESS                        0x0c00004c
#define WDT_RESET_OFFSET                         0x0000004c
#define WDT_RESET_VALUE_MSB                      0
#define WDT_RESET_VALUE_LSB                      0
#define WDT_RESET_VALUE_MASK                     0x00000001
#define WDT_RESET_VALUE_GET(x)                   (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB)
#define WDT_RESET_VALUE_SET(x)                   (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK)

#define INT_STATUS_ADDRESS                       0x0c000050
#define INT_STATUS_OFFSET                        0x00000050
#define INT_STATUS_TIMER_MSB                     14
#define INT_STATUS_TIMER_LSB                     14
#define INT_STATUS_TIMER_MASK                    0x00004000
#define INT_STATUS_TIMER_GET(x)                  (((x) & INT_STATUS_TIMER_MASK) >> INT_STATUS_TIMER_LSB)
#define INT_STATUS_TIMER_SET(x)                  (((x) << INT_STATUS_TIMER_LSB) & INT_STATUS_TIMER_MASK)
#define INT_STATUS_MAC_MSB                       13
#define INT_STATUS_MAC_LSB                       13
#define INT_STATUS_MAC_MASK                      0x00002000
#define INT_STATUS_MAC_GET(x)                    (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB)
#define INT_STATUS_MAC_SET(x)                    (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK)
#define INT_STATUS_MAILBOX_MSB                   12
#define INT_STATUS_MAILBOX_LSB                   12
#define INT_STATUS_MAILBOX_MASK                  0x00001000
#define INT_STATUS_MAILBOX_GET(x)                (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB)
#define INT_STATUS_MAILBOX_SET(x)                (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK)
#define INT_STATUS_RTC_ALARM_MSB                 11
#define INT_STATUS_RTC_ALARM_LSB                 11
#define INT_STATUS_RTC_ALARM_MASK                0x00000800
#define INT_STATUS_RTC_ALARM_GET(x)              (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB)
#define INT_STATUS_RTC_ALARM_SET(x)              (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK)
#define INT_STATUS_HF_TIMER_MSB                  10
#define INT_STATUS_HF_TIMER_LSB                  10
#define INT_STATUS_HF_TIMER_MASK                 0x00000400
#define INT_STATUS_HF_TIMER_GET(x)               (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB)
#define INT_STATUS_HF_TIMER_SET(x)               (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK)
#define INT_STATUS_LF_TIMER3_MSB                 9
#define INT_STATUS_LF_TIMER3_LSB                 9
#define INT_STATUS_LF_TIMER3_MASK                0x00000200
#define INT_STATUS_LF_TIMER3_GET(x)              (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB)
#define INT_STATUS_LF_TIMER3_SET(x)              (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK)
#define INT_STATUS_LF_TIMER2_MSB                 8
#define INT_STATUS_LF_TIMER2_LSB                 8
#define INT_STATUS_LF_TIMER2_MASK                0x00000100
#define INT_STATUS_LF_TIMER2_GET(x)              (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB)
#define INT_STATUS_LF_TIMER2_SET(x)              (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK)
#define INT_STATUS_LF_TIMER1_MSB                 7
#define INT_STATUS_LF_TIMER1_LSB                 7
#define INT_STATUS_LF_TIMER1_MASK                0x00000080
#define INT_STATUS_LF_TIMER1_GET(x)              (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB)
#define INT_STATUS_LF_TIMER1_SET(x)              (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK)
#define INT_STATUS_LF_TIMER0_MSB                 6
#define INT_STATUS_LF_TIMER0_LSB                 6
#define INT_STATUS_LF_TIMER0_MASK                0x00000040
#define INT_STATUS_LF_TIMER0_GET(x)              (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB)
#define INT_STATUS_LF_TIMER0_SET(x)              (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK)
#define INT_STATUS_KEYPAD_MSB                    5
#define INT_STATUS_KEYPAD_LSB                    5
#define INT_STATUS_KEYPAD_MASK                   0x00000020
#define INT_STATUS_KEYPAD_GET(x)                 (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB)
#define INT_STATUS_KEYPAD_SET(x)                 (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK)
#define INT_STATUS_SI_MSB                        4
#define INT_STATUS_SI_LSB                        4
#define INT_STATUS_SI_MASK                       0x00000010