mc_reg.h

Atheros Communications AR6001 WLAN Driver for SDIO installation Read Me March 26,2007 (based on

#define BANK1_CONFIG_TIMER3_MASK                 0x0000f000
#define BANK1_CONFIG_TIMER3_GET(x)               (((x) & BANK1_CONFIG_TIMER3_MASK) >> BANK1_CONFIG_TIMER3_LSB)
#define BANK1_CONFIG_TIMER3_SET(x)               (((x) << BANK1_CONFIG_TIMER3_LSB) & BANK1_CONFIG_TIMER3_MASK)
#define BANK1_CONFIG_TIMER2_MSB                  11
#define BANK1_CONFIG_TIMER2_LSB                  8
#define BANK1_CONFIG_TIMER2_MASK                 0x00000f00
#define BANK1_CONFIG_TIMER2_GET(x)               (((x) & BANK1_CONFIG_TIMER2_MASK) >> BANK1_CONFIG_TIMER2_LSB)
#define BANK1_CONFIG_TIMER2_SET(x)               (((x) << BANK1_CONFIG_TIMER2_LSB) & BANK1_CONFIG_TIMER2_MASK)
#define BANK1_CONFIG_TIMER1_MSB                  7
#define BANK1_CONFIG_TIMER1_LSB                  4
#define BANK1_CONFIG_TIMER1_MASK                 0x000000f0
#define BANK1_CONFIG_TIMER1_GET(x)               (((x) & BANK1_CONFIG_TIMER1_MASK) >> BANK1_CONFIG_TIMER1_LSB)
#define BANK1_CONFIG_TIMER1_SET(x)               (((x) << BANK1_CONFIG_TIMER1_LSB) & BANK1_CONFIG_TIMER1_MASK)
#define BANK1_CONFIG_TIMER0_MSB                  3
#define BANK1_CONFIG_TIMER0_LSB                  0
#define BANK1_CONFIG_TIMER0_MASK                 0x0000000f
#define BANK1_CONFIG_TIMER0_GET(x)               (((x) & BANK1_CONFIG_TIMER0_MASK) >> BANK1_CONFIG_TIMER0_LSB)
#define BANK1_CONFIG_TIMER0_SET(x)               (((x) << BANK1_CONFIG_TIMER0_LSB) & BANK1_CONFIG_TIMER0_MASK)

#define BANK1_READ_ADDRESS                       0x0c004018
#define BANK1_READ_OFFSET                        0x00000018
#define BANK1_READ_ENABLE_WAIT_MSB               31
#define BANK1_READ_ENABLE_WAIT_LSB               31
#define BANK1_READ_ENABLE_WAIT_MASK              0x80000000
#define BANK1_READ_ENABLE_WAIT_GET(x)            (((x) & BANK1_READ_ENABLE_WAIT_MASK) >> BANK1_READ_ENABLE_WAIT_LSB)
#define BANK1_READ_ENABLE_WAIT_SET(x)            (((x) << BANK1_READ_ENABLE_WAIT_LSB) & BANK1_READ_ENABLE_WAIT_MASK)
#define BANK1_READ_WAIT_EVENT_MSB                30
#define BANK1_READ_WAIT_EVENT_LSB                28
#define BANK1_READ_WAIT_EVENT_MASK               0x70000000
#define BANK1_READ_WAIT_EVENT_GET(x)             (((x) & BANK1_READ_WAIT_EVENT_MASK) >> BANK1_READ_WAIT_EVENT_LSB)
#define BANK1_READ_WAIT_EVENT_SET(x)             (((x) << BANK1_READ_WAIT_EVENT_LSB) & BANK1_READ_WAIT_EVENT_MASK)
#define BANK1_READ_END_EVENT_MSB                 26
#define BANK1_READ_END_EVENT_LSB                 24
#define BANK1_READ_END_EVENT_MASK                0x07000000
#define BANK1_READ_END_EVENT_GET(x)              (((x) & BANK1_READ_END_EVENT_MASK) >> BANK1_READ_END_EVENT_LSB)
#define BANK1_READ_END_EVENT_SET(x)              (((x) << BANK1_READ_END_EVENT_LSB) & BANK1_READ_END_EVENT_MASK)
#define BANK1_READ_BURST_END_EVENT_MSB           22
#define BANK1_READ_BURST_END_EVENT_LSB           20
#define BANK1_READ_BURST_END_EVENT_MASK          0x00700000
#define BANK1_READ_BURST_END_EVENT_GET(x)        (((x) & BANK1_READ_BURST_END_EVENT_MASK) >> BANK1_READ_BURST_END_EVENT_LSB)
#define BANK1_READ_BURST_END_EVENT_SET(x)        (((x) << BANK1_READ_BURST_END_EVENT_LSB) & BANK1_READ_BURST_END_EVENT_MASK)
#define BANK1_READ_BURST_START_EVENT_MSB         18
#define BANK1_READ_BURST_START_EVENT_LSB         16
#define BANK1_READ_BURST_START_EVENT_MASK        0x00070000
#define BANK1_READ_BURST_START_EVENT_GET(x)      (((x) & BANK1_READ_BURST_START_EVENT_MASK) >> BANK1_READ_BURST_START_EVENT_LSB)
#define BANK1_READ_BURST_START_EVENT_SET(x)      (((x) << BANK1_READ_BURST_START_EVENT_LSB) & BANK1_READ_BURST_START_EVENT_MASK)
#define BANK1_READ_EVENT3_DC_MSB                 15
#define BANK1_READ_EVENT3_DC_LSB                 15
#define BANK1_READ_EVENT3_DC_MASK                0x00008000
#define BANK1_READ_EVENT3_DC_GET(x)              (((x) & BANK1_READ_EVENT3_DC_MASK) >> BANK1_READ_EVENT3_DC_LSB)
#define BANK1_READ_EVENT3_DC_SET(x)              (((x) << BANK1_READ_EVENT3_DC_LSB) & BANK1_READ_EVENT3_DC_MASK)
#define BANK1_READ_EVENT3_BE_MSB                 14
#define BANK1_READ_EVENT3_BE_LSB                 14
#define BANK1_READ_EVENT3_BE_MASK                0x00004000
#define BANK1_READ_EVENT3_BE_GET(x)              (((x) & BANK1_READ_EVENT3_BE_MASK) >> BANK1_READ_EVENT3_BE_LSB)
#define BANK1_READ_EVENT3_BE_SET(x)              (((x) << BANK1_READ_EVENT3_BE_LSB) & BANK1_READ_EVENT3_BE_MASK)
#define BANK1_READ_EVENT3_OE_MSB                 13
#define BANK1_READ_EVENT3_OE_LSB                 13
#define BANK1_READ_EVENT3_OE_MASK                0x00002000
#define BANK1_READ_EVENT3_OE_GET(x)              (((x) & BANK1_READ_EVENT3_OE_MASK) >> BANK1_READ_EVENT3_OE_LSB)
#define BANK1_READ_EVENT3_OE_SET(x)              (((x) << BANK1_READ_EVENT3_OE_LSB) & BANK1_READ_EVENT3_OE_MASK)
#define BANK1_READ_EVENT3_CS_MSB                 12
#define BANK1_READ_EVENT3_CS_LSB                 12
#define BANK1_READ_EVENT3_CS_MASK                0x00001000
#define BANK1_READ_EVENT3_CS_GET(x)              (((x) & BANK1_READ_EVENT3_CS_MASK) >> BANK1_READ_EVENT3_CS_LSB)
#define BANK1_READ_EVENT3_CS_SET(x)              (((x) << BANK1_READ_EVENT3_CS_LSB) & BANK1_READ_EVENT3_CS_MASK)
#define BANK1_READ_EVENT2_DC_MSB                 11
#define BANK1_READ_EVENT2_DC_LSB                 11
#define BANK1_READ_EVENT2_DC_MASK                0x00000800
#define BANK1_READ_EVENT2_DC_GET(x)              (((x) & BANK1_READ_EVENT2_DC_MASK) >> BANK1_READ_EVENT2_DC_LSB)
#define BANK1_READ_EVENT2_DC_SET(x)              (((x) << BANK1_READ_EVENT2_DC_LSB) & BANK1_READ_EVENT2_DC_MASK)
#define BANK1_READ_EVENT2_BE_MSB                 10
#define BANK1_READ_EVENT2_BE_LSB                 10
#define BANK1_READ_EVENT2_BE_MASK                0x00000400
#define BANK1_READ_EVENT2_BE_GET(x)              (((x) & BANK1_READ_EVENT2_BE_MASK) >> BANK1_READ_EVENT2_BE_LSB)
#define BANK1_READ_EVENT2_BE_SET(x)              (((x) << BANK1_READ_EVENT2_BE_LSB) & BANK1_READ_EVENT2_BE_MASK)
#define BANK1_READ_EVENT2_OE_MSB                 9
#define BANK1_READ_EVENT2_OE_LSB                 9
#define BANK1_READ_EVENT2_OE_MASK                0x00000200
#define BANK1_READ_EVENT2_OE_GET(x)              (((x) & BANK1_READ_EVENT2_OE_MASK) >> BANK1_READ_EVENT2_OE_LSB)
#define BANK1_READ_EVENT2_OE_SET(x)              (((x) << BANK1_READ_EVENT2_OE_LSB) & BANK1_READ_EVENT2_OE_MASK)
#define BANK1_READ_EVENT2_CS_MSB                 8
#define BANK1_READ_EVENT2_CS_LSB                 8
#define BANK1_READ_EVENT2_CS_MASK                0x00000100
#define BANK1_READ_EVENT2_CS_GET(x)              (((x) & BANK1_READ_EVENT2_CS_MASK) >> BANK1_READ_EVENT2_CS_LSB)
#define BANK1_READ_EVENT2_CS_SET(x)              (((x) << BANK1_READ_EVENT2_CS_LSB) & BANK1_READ_EVENT2_CS_MASK)
#define BANK1_READ_EVENT1_DC_MSB                 7
#define BANK1_READ_EVENT1_DC_LSB                 7
#define BANK1_READ_EVENT1_DC_MASK                0x00000080
#define BANK1_READ_EVENT1_DC_GET(x)              (((x) & BANK1_READ_EVENT1_DC_MASK) >> BANK1_READ_EVENT1_DC_LSB)
#define BANK1_READ_EVENT1_DC_SET(x)              (((x) << BANK1_READ_EVENT1_DC_LSB) & BANK1_READ_EVENT1_DC_MASK)
#define BANK1_READ_EVENT1_BE_MSB                 6
#define BANK1_READ_EVENT1_BE_LSB                 6
#define BANK1_READ_EVENT1_BE_MASK                0x00000040
#define BANK1_READ_EVENT1_BE_GET(x)              (((x) & BANK1_READ_EVENT1_BE_MASK) >> BANK1_READ_EVENT1_BE_LSB)
#define BANK1_READ_EVENT1_BE_SET(x)              (((x) << BANK1_READ_EVENT1_BE_LSB) & BANK1_READ_EVENT1_BE_MASK)
#define BANK1_READ_EVENT1_OE_MSB                 5
#define BANK1_READ_EVENT1_OE_LSB                 5
#define BANK1_READ_EVENT1_OE_MASK                0x00000020
#define BANK1_READ_EVENT1_OE_GET(x)              (((x) & BANK1_READ_EVENT1_OE_MASK) >> BANK1_READ_EVENT1_OE_LSB)
#define BANK1_READ_EVENT1_OE_SET(x)              (((x) << BANK1_READ_EVENT1_OE_LSB) & BANK1_READ_EVENT1_OE_MASK)
#define BANK1_READ_EVENT1_CS_MSB                 4
#define BANK1_READ_EVENT1_CS_LSB                 4
#define BANK1_READ_EVENT1_CS_MASK                0x00000010
#define BANK1_READ_EVENT1_CS_GET(x)              (((x) & BANK1_READ_EVENT1_CS_MASK) >> BANK1_READ_EVENT1_CS_LSB)
#define BANK1_READ_EVENT1_CS_SET(x)              (((x) << BANK1_READ_EVENT1_CS_LSB) & BANK1_READ_EVENT1_CS_MASK)
#define BANK1_READ_EVENT0_DC_MSB                 3
#define BANK1_READ_EVENT0_DC_LSB                 3
#define BANK1_READ_EVENT0_DC_MASK                0x00000008
#define BANK1_READ_EVENT0_DC_GET(x)              (((x) & BANK1_READ_EVENT0_DC_MASK) >> BANK1_READ_EVENT0_DC_LSB)
#define BANK1_READ_EVENT0_DC_SET(x)              (((x) << BANK1_READ_EVENT0_DC_LSB) & BANK1_READ_EVENT0_DC_MASK)
#define BANK1_READ_EVENT0_BE_MSB                 2
#define BANK1_READ_EVENT0_BE_LSB                 2
#define BANK1_READ_EVENT0_BE_MASK                0x00000004
#define BANK1_READ_EVENT0_BE_GET(x)              (((x) & BANK1_READ_EVENT0_BE_MASK) >> BANK1_READ_EVENT0_BE_LSB)
#define BANK1_READ_EVENT0_BE_SET(x)              (((x) << BANK1_READ_EVENT0_BE_LSB) & BANK1_READ_EVENT0_BE_MASK)
#define BANK1_READ_EVENT0_OE_MSB                 1
#define BANK1_READ_EVENT0_OE_LSB                 1
#define BANK1_READ_EVENT0_OE_MASK                0x00000002
#define BANK1_READ_EVENT0_OE_GET(x)              (((x) & BANK1_READ_EVENT0_OE_MASK) >> BANK1_READ_EVENT0_OE_LSB)
#define BANK1_READ_EVENT0_OE_SET(x)              (((x) << BANK1_READ_EVENT0_OE_LSB) & BANK1_READ_EVENT0_OE_MASK)
#define BANK1_READ_EVENT0_CS_MSB                 0
#define BANK1_READ_EVENT0_CS_LSB                 0
#define BANK1_READ_EVENT0_CS_MASK                0x00000001
#define BANK1_READ_EVENT0_CS_GET(x)              (((x) & BANK1_READ_EVENT0_CS_MASK) >> BANK1_READ_EVENT0_CS_LSB)
#define BANK1_READ_EVENT0_CS_SET(x)              (((x) << BANK1_READ_EVENT0_CS_LSB) & BANK1_READ_EVENT0_CS_MASK)

#define BANK1_WRITE_ADDRESS                      0x0c00401c
#define BANK1_WRITE_OFFSET                       0x0000001c
#define BANK1_WRITE_ENABLE_WAIT_MSB              31
#define BANK1_WRITE_ENABLE_WAIT_LSB              31
#define BANK1_WRITE_ENABLE_WAIT_MASK             0x80000000
#define BANK1_WRITE_ENABLE_WAIT_GET(x)           (((x) & BANK1_WRITE_ENABLE_WAIT_MASK) >> BANK1_WRITE_ENABLE_WAIT_LSB)
#define BANK1_WRITE_ENABLE_WAIT_SET(x)           (((x) << BANK1_WRITE_ENABLE_WAIT_LSB) & BANK1_WRITE_ENABLE_WAIT_MASK)
#define BANK1_WRITE_WAIT_EVENT_MSB               30
#define BANK1_WRITE_WAIT_EVENT_LSB               28
#define BANK1_WRITE_WAIT_EVENT_MASK              0x70000000
#define BANK1_WRITE_WAIT_EVENT_GET(x)            (((x) & BANK1_WRITE_WAIT_EVENT_MASK) >> BANK1_WRITE_WAIT_EVENT_LSB)
#define BANK1_WRITE_WAIT_EVENT_SET(x)            (((x) << BANK1_WRITE_WAIT_EVENT_LSB) & BANK1_WRITE_WAIT_EVENT_MASK)
#define BANK1_WRITE_END_EVENT_MSB                26
#define BANK1_WRITE_END_EVENT_LSB                24
#define BANK1_WRITE_END_EVENT_MASK               0x07000000
#define BANK1_WRITE_END_EVENT_GET(x)             (((x) & BANK1_WRITE_END_EVENT_MASK) >> BANK1_WRITE_END_EVENT_LSB)
#define BANK1_WRITE_END_EVENT_SET(x)             (((x) << BANK1_WRITE_END_EVENT_LSB) & BANK1_WRITE_END_EVENT_MASK)
#define BANK1_WRITE_BURST_END_EVENT_MSB          22
#define BANK1_WRITE_BURST_END_EVENT_LSB          20
#define BANK1_WRITE_BURST_END_EVENT_MASK         0x00700000
#define BANK1_WRITE_BURST_END_EVENT_GET(x)       (((x) & BANK1_WRITE_BURST_END_EVENT_MASK) >> BANK1_WRITE_BURST_END_EVENT_LSB)
#define BANK1_WRITE_BURST_END_EVENT_SET(x)       (((x) << BANK1_WRITE_BURST_END_EVENT_LSB) & BANK1_WRITE_BURST_END_EVENT_MASK)
#define BANK1_WRITE_BURST_START_EVENT_MSB        18
#define BANK1_WRITE_BURST_START_EVENT_LSB        16
#define BANK1_WRITE_BURST_START_EVENT_MASK       0x00070000
#define BANK1_WRITE_BURST_START_EVENT_GET(x)     (((x) & BANK1_WRITE_BURST_START_EVENT_MASK) >> BANK1_WRITE_BURST_START_EVENT_LSB)
#define BANK1_WRITE_BURST_START_EVENT_SET(x)     (((x) << BANK1_WRITE_BURST_START_EVENT_LSB) & BANK1_WRITE_BURST_START_EVENT_MASK)
#define BANK1_WRITE_EVENT3_BE_MSB                14
#define BANK1_WRITE_EVENT3_BE_LSB                14
#define BANK1_WRITE_EVENT3_BE_MASK               0x00004000
#define BANK1_WRITE_EVENT3_BE_GET(x)             (((x) & BANK1_WRITE_EVENT3_BE_MASK) >> BANK1_WRITE_EVENT3_BE_LSB)
#define BANK1_WRITE_EVENT3_BE_SET(x)             (((x) << BANK1_WRITE_EVENT3_BE_LSB) & BANK1_WRITE_EVENT3_BE_MASK)
#define BANK1_WRITE_EVENT3_WE_MSB                13
#define BANK1_WRITE_EVENT3_WE_LSB                13
#define BANK1_WRITE_EVENT3_WE_MASK               0x00002000
#define BANK1_WRITE_EVENT3_WE_GET(x)             (((x) & BANK1_WRITE_EVENT3_WE_MASK) >> BANK1_WRITE_EVENT3_WE_LSB)
#define BANK1_WRITE_EVENT3_WE_SET(x)             (((x) << BANK1_WRITE_EVENT3_WE_LSB) & BANK1_WRITE_EVENT3_WE_MASK)
#define BANK1_WRITE_EVENT3_CS_MSB                12
#define BANK1_WRITE_EVENT3_CS_LSB                12
#define BANK1_WRITE_EVENT3_CS_MASK               0x00001000
#define BANK1_WRITE_EVENT3_CS_GET(x)             (((x) & BANK1_WRITE_EVENT3_CS_MASK) >> BANK1_WRITE_EVENT3_CS_LSB)
#define BANK1_WRITE_EVENT3_CS_SET(x)             (((x) << BANK1_WRITE_EVENT3_CS_LSB) & BANK1_WRITE_EVENT3_CS_MASK)
#define BANK1_WRITE_EVENT2_BE_MSB                10
#define BANK1_WRITE_EVENT2_BE_LSB                10
#define BANK1_WRITE_EVENT2_BE_MASK               0x00000400
#define BANK1_WRITE_EVENT2_BE_GET(x)             (((x) & BANK1_WRITE_EVENT2_BE_MASK) >> BANK1_WRITE_EVENT2_BE_LSB)