mcbsp.h

DSP的集成开发

#define MCBSP_RX      1
#define MCBSP_TX      2
#define MCBSP_BOTH    3

/* Multi-channel Control Register (MCCR) bits */
#define RMCM          0
#define RPABLK        5
#define RPABLK_SZ     2
#define RPBBLK        7
#define RPBBLK_SZ     2
#define XMCM          16
#define XMCM_SZ       2
#define XPABLK        21
#define XPABLK_SZ     2
#define XPBBLK        23
#define XPBBLK_SZ     2

/* Receive Channel Enable Register (RCER) bits */
#define RCEA          0
#define RCEA_SZ       16
#define RCEB          16
#define RCEB_SZ       16

/* Transmit Channel Enable Register (XCER) bits */
#define XCEA          0
#define XCEA_SZ       16
#define XCEB          16
#define XCEB_SZ       16

/* CONFIGURATION REGISTER BIT and BITFIELD values                             */
/* Serial Port Control Register SPCR                                          */

#define INTM_RDY            0x00     /* R/X INT driven by R/X RDY             */
#define INTM_BLOCK          0x01     /* R/X INT driven by new multichannel blk*/
#define INTM_FRAME          0x02     /* R/X INT driven by new frame sync      */
#define INTM_SYNCERR        0x03     /* R/X INT generated by R/X SYNCERR      */

#define DLB_ENABLE          0x01     /* Enable Digital Loopback Mode          */
#define DLB_DISABLE         0x00     /* Disable Digital Loopback Mode         */

#define RXJUST_RJZF         0x00     /* Receive Right Justify Zero Fill       */
#define RXJUST_RJSE         0x01     /* Receive Right Justify Sign Extend     */
#define RXJUST_LJZF         0x02     /* Receive Left Justify Zero Fill        */

/* Pin Control Register PCR                                                   */

#define CLKR_POL_RISING     0x01     /* R Data Sampled on Rising Edge of CLKR */
#define CLKR_POL_FALLING    0x00     /* R Data Sampled on Falling Edge of CLKR*/
#define CLKX_POL_RISING     0x00     /* X Data Sent on Rising Edge of CLKX    */
#define CLKX_POL_FALLING    0x01     /* X Data Sent on Falling Edge of CLKX   */
#define FSYNC_POL_HIGH      0x00     /* Frame Sync Pulse Active High          */
#define FSYNC_POL_LOW       0x01     /* Frame Sync Pulse Active Low           */

#define CLK_MODE_EXT        0x00     /* Clock derived from external source    */
#define CLK_MODE_INT        0x01     /* Clock derived from internal source    */

#define FSYNC_MODE_EXT      0x00     /* Frame Sync derived from external src  */
#define FSYNC_MODE_INT      0x01     /* Frame Sync dervived from internal src */

/* Transmit Receive Control Register XCR/RCR                                  */

#define SINGLE_PHASE        0x00     /* Selects single phase frames           */
#define DUAL_PHASE          0x01     /* Selects dual phase frames             */

#define MAX_FRAME_LENGTH    0x7f     /* maximum number of words per frame     */

#define WORD_LENGTH_8       0x00     /* 8 bit word length (requires filling)  */
#define WORD_LENGTH_12      0x01     /* 12 bit word length       ""           */
#define WORD_LENGTH_16      0x02     /* 16 bit word length       ""           */
#define WORD_LENGTH_20      0x03     /* 20 bit word length       ""           */
#define WORD_LENGTH_24      0x04     /* 24 bit word length       ""           */
#define WORD_LENGTH_32      0x05     /* 32 bit word length (matches DRR DXR sz*/

#define MAX_WORD_LENGTH     WORD_LENGTH_32

#define NO_COMPAND_MSB_1ST  0x00     /* No Companding, Data XFER starts w/MSb */
#define NO_COMPAND_LSB_1ST  0x01     /* No Companding, Data XFER starts w/LSb */
#define COMPAND_ULAW        0x02     /* Compand ULAW, 8 bit word length only  */
#define COMPAND_ALAW        0x03     /* Compand ALAW, 8 bit word length only  */

#define FRAME_IGNORE        0x01     /* Ignore frame sync pulses after 1st    */
#define NO_FRAME_IGNORE     0x00     /* Utilize frame sync pulses             */

#define DATA_DELAY0         0x00     /* 1st bit in same clk period as fsync   */
#define DATA_DELAY1         0x01     /* 1st bit 1 clk period after fsync      */
#define DATA_DELAY2         0x02     /* 1st bit 2 clk periods after fsync     */
  
/* Sample Rate Generator Register SRGR */

#define MAX_SRG_CLK_DIV     0xFF     /* max value to divide Sample Rate Gen Cl*/
#define MAX_FRAME_WIDTH     0xFF     /* maximum FSG width in CLKG periods     */
#define MAX_FRAME_PERIOD    0x0FFF   /* FSG period in CLKG periods            */

#define FSX_DXR_TO_XSR      0x00     /* Transmit FSX due to DXR to XSR copy   */
#define FSX_FSG             0x01     /* Transmit FSX due to FSG               */

#define CLK_MODE_CLKS       0x00     /* Clock derived from CLKS source        */
#define CLK_MODE_CPU        0x01     /* Clock derived from CPU clock source   */

#define CLKS_POL_FALLING    0x01     /* falling edge generates CLKG and FSG   */
#define CLKS_POL_RISING     0x00     /* rising edge generates CLKG and FSG    */

#define GSYNC_OFF           0x00     /* CLKG always running                   */
#define GSYNC_ON            0x01     /* CLKG and FSG synched to FSR           */ 

/******************************************************************************/
/* MCBSP_BYTES_PER_WORD - return # of bytes required to hold #                */
/*                        of bits indicated by wdlen                          */
/******************************************************************************/
#define MCBSP_BYTES_PER_WORD(wdlen) \
        ( (wdlen) == WORD_LENGTH_32 ? 4 : (int)(((wdlen) + 2) / 2) )

/******************************************************************************/
/* MCBSP_ENABLE(unsigned short port_no, unsigned short type) -                */
/*            starts serial port receive and/or transmit                      */
/*            type= 1 rx, type= 2 tx, type= 3 both                            */
/******************************************************************************/
#define MCBSP_ENABLE(port_no,type)\
     (*(unsigned int *)MCBSP_SPCR_ADDR(port_no) |= \
     ((type % 2) * MASK_BIT(RRST)) | ((type/2) * MASK_BIT(XRST)))

/******************************************************************************/
/* MCBSP_TX_RESET() - reset transmit side of serial port                      */
/******************************************************************************/
#define MCBSP_TX_RESET(port_no)\
     (*(unsigned int *)MCBSP_SPCR_ADDR(port_no) &= ~MASK_BIT(XRST))
    

/******************************************************************************/
/* MCBSP_RX_RESET() - reset receive side of serial port                       */
/******************************************************************************/
#define MCBSP_RX_RESET(port_no)\
    (*(unsigned int *)MCBSP_SPCR_ADDR(port_no) &= ~MASK_BIT(RRST))

/******************************************************************************/
/* MCBSP_READ() - read data value from serial port                            */
/******************************************************************************/
#define MCBSP_READ(port_no)\
     (*(unsigned int *)(MCBSP_DRR_ADDR(port_no)))

/******************************************************************************/
/* MCBSP_WRITE() - write data value to serial port transmit reg               */
/******************************************************************************/
#define MCBSP_WRITE(port_no, data)\
     (*(unsigned int *)(MCBSP_DXR_ADDR(port_no)) = (unsigned int) data)

/******************************************************************************/
/* MCBSP_IO_ENABLE() - place port in general purpose I/O mode                 */
/******************************************************************************/
#define MCBSP_IO_ENABLE(port_no) \
        { MCBSP_TX_RESET(port_no); MCBSP_RX_RESET(port_no); \
          RESET_FIELD(MCBSP_PCR_ADDR(port_no),RIOEN,2); }

/******************************************************************************/
/* MCBSP_IO_DISABLE() - take port out of general purpose I/O mode             */
/******************************************************************************/
#define MCBSP_IO_DISABLE(port_no) \
        SET_FIELD(MCBSP_PCR_ADDR(port_no),RIOEN,2)

/******************************************************************************/
/* MCBSP_FRAME_SYNC_ENABLE - sets FRST bit in SPCR                            */
/******************************************************************************/
#define MCBSP_FRAME_SYNC_ENABLE(port_no) \
        (SET_BIT(MCBSP_SPCR_ADDR(port_no),FRST))

/******************************************************************************/
/* MCBSP_FRAME_SYNC_RESET - clrs FRST bit in SPCR                             */
/******************************************************************************/
#define MCBSP_FRAME_SYNC_RESET(port_no) \
        (RESET_BIT(MCBSP_SPCR_ADDR(port_no),FRST))

/******************************************************************************/
/* MCBSP_SAMPLE_RATE_ENABLE - sets GRST bit in SPCR                           */
/******************************************************************************/
#define MCBSP_SAMPLE_RATE_ENABLE(port_no) \
        (SET_BIT(MCBSP_SPCR_ADDR(port_no),GRST))

/******************************************************************************/
/* MCBSP_SAMPLE_RATE_RESET - clrs GRST bit in SPCR                            */
/******************************************************************************/
#define MCBSP_SAMPLE_RATE_RESET(port_no) \
        (RESET_BIT(MCBSP_SPCR_ADDR(port_no),GRST))

/******************************************************************************/
/* MCBSP_RRDY - returns selected ports RRDY                                   */
/******************************************************************************/
#define MCBSP_RRDY(port_no) \
        (GET_BIT(MCBSP_SPCR_ADDR(port_no),RRDY))

/******************************************************************************/
/* MCBSP_XRDY - returns selected ports XRDY                                   */
/******************************************************************************/
#define MCBSP_XRDY(port_no) \
        (GET_BIT(MCBSP_SPCR_ADDR(port_no),XRDY))

/******************************************************************************/
/* MCBSP_LOOPBACK_ENABLE - places selected port in loopback                   */
/******************************************************************************/
#define MCBSP_LOOPBACK_ENABLE(port_no) \
        (SET_BIT(MCBSP_SPCR_ADDR(port_no),DLB))

/******************************************************************************/
/* MCBSP_LOOPBACK_DISABLE - takes port out of DLB                             */
/******************************************************************************/
#define MCBSP_LOOPBACK_DISABLE(port_no) \
        (RESET_BIT(MCBSP_SPCR_ADDR(port_no),DLB))

/*----------------------------------------------------------------------------*/
/* GLOBAL VARIABLES                                                           */
/*----------------------------------------------------------------------------*/

/*----------------------------------------------------------------------------*/
/* FUNCTIONS                                                                  */
/*----------------------------------------------------------------------------*/

__INLINE void mcbsp_init(unsigned short port_no,
                         unsigned int spcr_ctrl,
                         unsigned int rcr_ctrl,
                         unsigned int xcr_ctrl, 
                         unsigned int srgr_ctrl,
                         unsigned int mcr_ctrl, 
                         unsigned int rcer_ctrl,
                         unsigned int xcer_ctrl, 
                         unsigned int pcr_ctrl);


#ifdef _INLINE
/******************************************************************/
/* mcbsp_init - initialize and start serial port operation        */
/*                                                                */
/******************************************************************/
static inline void mcbsp_init(unsigned short port_no,
                              unsigned int spcr_ctrl,
                              unsigned int rcr_ctrl,
                              unsigned int xcr_ctrl, 
                              unsigned int srgr_ctrl,
                              unsigned int mcr_ctrl, 
                              unsigned int rcer_ctrl,
                              unsigned int xcer_ctrl, 
                              unsigned int pcr_ctrl)
{
   unsigned int *port = (unsigned int *)(MCBSP_ADDR(port_no));

   /****************************************************************/
   /* Place port in reset - setting XRST & RRST to 0               */
   /****************************************************************/
   *(port + 2) 	&= ~(MASK_BIT(RRST) | MASK_BIT(XRST));

   /****************************************************************/
   /* Set values of all control reigsters                          */
   /****************************************************************/
   *(port + 3) = rcr_ctrl;
   *(port + 4) = xcr_ctrl;
   *(port + 5) = srgr_ctrl;
   *(port + 6) = mcr_ctrl;
   *(port + 7) = rcer_ctrl;
   *(port + 8) = xcer_ctrl;
   *(port + 9) = pcr_ctrl;

   *(port + 2) = ~(MASK_BIT(RRST) | MASK_BIT(XRST)) & (spcr_ctrl);
   *(port + 2) |= (MASK_BIT(RRST) | MASK_BIT(XRST)) & (spcr_ctrl);
}
#else
void mcbsp_init(unsigned short port_no,
                              unsigned int spcr_ctrl,
                              unsigned int rcr_ctrl,
                              unsigned int xcr_ctrl, 
                              unsigned int srgr_ctrl,
                              unsigned int mcr_ctrl, 
                              unsigned int rcer_ctrl,
                              unsigned int xcer_ctrl, 
                              unsigned int pcr_ctrl)
{
   unsigned int *port = (unsigned int *)(MCBSP_ADDR(port_no));

   /****************************************************************/
   /* Place port in reset - setting XRST & RRST to 0               */
   /****************************************************************/
   *(port + 2) 	&= ~(MASK_BIT(RRST) | MASK_BIT(XRST));

   /****************************************************************/
   /* Set values of all control reigsters                          */
   /****************************************************************/
   *(port + 3) = rcr_ctrl;
   *(port + 4) = xcr_ctrl;
   *(port + 5) = srgr_ctrl;
   *(port + 6) = mcr_ctrl;
   *(port + 7) = rcer_ctrl;
   *(port + 8) = xcer_ctrl;
   *(port + 9) = pcr_ctrl;

   *(port + 2) = ~(MASK_BIT(RRST) | MASK_BIT(XRST)) & (spcr_ctrl);
   *(port + 2) |= (MASK_BIT(RRST) | MASK_BIT(XRST)) & (spcr_ctrl);
}
#endif

#ifdef __INLINE
#undef __INLINE
#endif

#endif /* _MCBSP_H_ */