📄 emifa.h
字号:
/******************************************************************************/
/* EMIF.H - TMS320C6x Peripheral Support Library EMIF Support */
/* */
/* This file provides the header for the DSP's EMIF support. */
/* */
/* MACRO FUNCTIONS: */
/* SDRAM_REFRESH_ENABLE() - Enable SDRAM refresh cycles */
/* SDRAM_REFRESH_DISABLE() - Disable SDRAM refresh cycles */
/* SDRAM_REFRESH_PERIOD() - Assigns refresh period for SDRAM */
/* SDRAM_INIT() - Perform initialization sequence for SDRAM */
/* EMIF_GET_MAP_MODE() - Return value of MAP bit in EMIF global ctrl */
/* */
/* FUNCTIONS: */
/* emif_init() - Sets all EMIF registers to parameter values */
/* */
/* DATE DESCRIPTION */
/* ------- ------------------------------------------------------------- */
/* 11MAY98 Removed #define TA and #define TA_SZ */
/* -----> TA is no longer supported. */
/* */
/* 11MAY98 Removed #define CLK2INV and #define SDCINV */
/* -----> These bitfields are no longer supported. */
/* */
/* 11MAY98 Changed "LOAD_FIELD(EMIF_SDRAM_REF_ADDR, val)" */
/* to "LOAD_FIELD(EMIF_SDRAM_REF_ADDR, val, PERIOD,PERIOD_SZ)"*/
/* -----> Fields were left out of the LOAD_FIELD macro call */
/* */
/* 11MAY98 Changed "#define WRTIE_STROBE_SZ" */
/* to "#define WRITE_STROBE_SZ" */
/* -----> Misspelling */
/* 修改日期：2006.10.18 */
/* 修改人 ：李学广 */
/******************************************************************************/
#ifndef _EMIFA_H_
#define _EMIFA_H_
#include "regs.h" /* EMIF Register Addresses and bitfield definitions */
#if _INLINE
#define __INLINE static inline
#else
#define __INLINE
#endif
/******************************************************************************/
/****************************** EMIF REGISTERS ********************************/
#define EMIFA_GCTRL_ADDR 0x01800000
#define EMIFA_CE0_CTRL_ADDR 0x01800008
#define EMIFA_CE1_CTRL_ADDR 0x01800004
#define EMIFA_CE2_CTRL_ADDR 0x01800010
#define EMIFA_CE3_CTRL_ADDR 0x01800014
#define EMIFA_SDRAM_CTRL_ADDR 0x01800018
#define EMIFA_SDRAM_REF_ADDR 0x0180001C
#define EMIFA_SDRAM_EXT_ADDR 0x01800020
#define EMIFA_PDT_CTL_ADDR 0x01800040
#define EMIFA_CE0_SEC_CTRL_ADDR 0x01800048
#define EMIFA_CE1_SEC_CTRL_ADDR 0x01800044
#define EMIFA_CE2_SEC_CTRL_ADDR 0x01800050
#define EMIFA_CE3_SEC_CTRL_ADDR 0x01800054
#define EMIFA_GCTRL (*(volatile unsigned int *)EMIFA_GCTRL_ADDR)
#define EMIFA_CE0_CTRL (*(volatile unsigned int *)EMIFA_CE0_CTRL_ADDR)
#define EMIFA_CE1_CTRL (*(volatile unsigned int *)EMIFA_CE1_CTRL_ADDR)
#define EMIFA_CE2_CTRL (*(volatile unsigned int *)EMIFA_CE2_CTRL_ADDR)
#define EMIFA_CE3_CTRL (*(volatile unsigned int *)EMIFA_CE3_CTRL_ADDR)
#define EMIFA_SDRAM_CTRL (*(volatile unsigned int *)EMIFA_SDRAM_CTRL_ADDR)
#define EMIFA_SDRAM_REF (*(volatile unsigned int *)EMIFA_SDRAM_REF_ADDR)
/* EMIF Global Control Register Bits C6416专用 */
/* EMIF 全局控制寄存器（GBLCTL） */
#define MAP 0
#define RBTR8 1
#define SSCRT 2
#define CLK6EN 3
#define CLK4EN 4
#define EK1EN 5
#define EK1HZ 6
#define NOHOLD 7
#define HOLDA 8
#define HOLD 9
#define ARDY 10
#define BUSREQ 11
#define BRMODE 13
#define EK2EN 16
#define EK2HZ 17
#define EN2RATE 18
#define EN2RATE_SZ 2
/* EMIF CE0/1/2/3 Control Register Bits */
/* EMIF CE空间控制寄存器(CECTL0~3)*/
#define READ_HOLD 0
#define READ_HOLD_SZ 2
#define MTYPE 4
#define MTYPE_SZ 4
#define READ_STROBE 8
#define READ_STROBE_SZ 6
#define READ_SETUP 16
#define READ_SETUP_SZ 4
#define WRITE_HOLD 20
#define WRITE_HOLD_SZ 2
#define WRITE_STROBE 22
#define WRITE_STROBE_SZ 6
#define WRITE_SETUP 28
#define WRITE_SETUP_SZ 4
#define TA 14
#define TA_SZ 2
/* EMIF SDRAM Control Register Bits */
/* EMIF SDRAM 控制寄存器（SDCTL） */
#define SLFRFR 0
#define TRC 12
#define TRC_SZ 4
#define TRP 16
#define TRP_SZ 4
#define TRCD 20
#define TRCD_SZ 4
#define INIT 24
#define RFEN 25
#define SDCSZ 26
#define SDCSZ_SZ 2
#define SDRSZ 28
#define SDRSZ_SZ 2
#define SDBSZ 30
/* EMIF SDRAM Timing Register Bits */
/* EMIF SDRAM 时序寄存器（SDTIM) */
#define PERIOD 0
#define PERIOD_SZ 12
#define COUNTER 12
#define COUNTER_SZ 12
#define XRFR 24
#define XRFR_SZ 2
/* EMIF Global Control Register Bitfield Values */
/* EMIF CE Space Control Register Bitfield Values */
#define MTYPE_8ROM 0x00 /* 8 bit wide ROM */
#define MTYPE_16ROM 0x01 /* 16 bit wide ROM */
#define MTYPE_32ASYNC 0x02 /* 32 bit asynchronous interface */
#define MTYPE_32SDRAM 0x03 /* 32 bit SDRAM */
#define MTYPE_32SBSRAM 0x04 /* 32 bit SBSRAM */
/*---------------------------------------------------------------------------*/
/* MACRO FUNCTIONS */
/*---------------------------------------------------------------------------*/
#define SDRAM_REFRESH_ENABLE() \
SET_BIT(EMIFA_SDRAM_CTRL_ADDR,RFEN)
#define SDRAM_REFRESH_DISABLE() \
RESET_BIT(EMIFA_SDRAM_CTRL_ADDR,RFEN)
#define SDRAM_REFRESH_PERIOD(val) \
LOAD_FIELD(EMIFA_SDRAM_REF_ADDR,val,PERIOD,PERIOD_SZ)
#define SDRAM_INIT() \
SET_BIT(EMIFA_SDRAM_CTRL_ADDR,INIT)
#define EMIF_GET_MAP_MODE() \
GET_BIT(EMIFA_GCTRL_ADDR,MAP)
__INLINE
far void emifa_init(unsigned int g_ctrl,
unsigned int ce0_ctrl,
unsigned int ce1_ctrl,
unsigned int ce2_ctrl,
unsigned int ce3_ctrl,
unsigned int sdram_ctrl,
unsigned int sdram_refresh
);
//#if _INLINE
__INLINE
void emifa_init(unsigned int g_ctrl,
unsigned int ce0_ctrl,
unsigned int ce1_ctrl,
unsigned int ce2_ctrl,
unsigned int ce3_ctrl,
unsigned int sdram_ctrl,
unsigned int sdram_refresh
)
{
REG_WRITE(EMIFA_GCTRL_ADDR, g_ctrl);
REG_WRITE(EMIFA_CE0_CTRL_ADDR, ce0_ctrl);
REG_WRITE(EMIFA_CE1_CTRL_ADDR, ce1_ctrl);
REG_WRITE(EMIFA_CE2_CTRL_ADDR, ce2_ctrl);
REG_WRITE(EMIFA_CE3_CTRL_ADDR, ce3_ctrl);
REG_WRITE(EMIFA_SDRAM_CTRL_ADDR, sdram_ctrl);
REG_WRITE(EMIFA_SDRAM_REF_ADDR, sdram_refresh);
}
//#endif /* _INLINE */
#ifdef __INLINE
#undef __INLINE
#endif
#endif /* _EMIF_H_ */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -