📄 io.lst
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146 1
147 1 P0L = 0x0000; // load data register
148 1 POCON0L = 0x0000; // load output control register
149 1 DP0L = 0x0000; // load direction register
150 1
151 1 /// -----------------------------------------------------------------------
152 1 /// Configuration of Port P1H:
153 1 /// -----------------------------------------------------------------------
154 1 /// - no pin of port P1H is used
155 1
156 1 P1H = 0x0000; // load data register
157 1 ALTSEL0P1H = 0x0000; // load alternate output function select
158 1 // register 0
159 1 POCON1H = 0x0000; // load output control register
160 1 DP1H = 0x0000; // load direction register
161 1
162 1 /// -----------------------------------------------------------------------
163 1 /// Configuration of Port P1L:
164 1 /// -----------------------------------------------------------------------
165 1 /// P1L.0 is used as general purpose output
166 1 /// - the pin status is low level
167 1 /// P1L.1 is used as general purpose output
168 1 /// - the pin status is low level
169 1 /// P1L.2 is used as general purpose output
170 1 /// - the pin status is low level
171 1 /// P1L.3 is used as general purpose output
172 1 /// - the pin status is low level
173 1 /// P1L.4 is used as general purpose output
174 1 /// - the pin status is low level
175 1 /// P1L.5 is used as general purpose output
176 1 /// - the pin status is low level
177 1 /// P1L.6 is used as general purpose output
178 1 /// - the pin status is low level
179 1 /// P1L.7 is used as general purpose output
C166 COMPILER V6.08, IO 09/12/2008 14:54:07 PAGE 4
180 1 /// - the pin status is low level
181 1
182 1 /// P1L.0 - P1L.3 output driver characteristic: strong driver
183 1 /// P1L.4 - P1L.7 output driver characteristic: strong driver
184 1
185 1 /// P1L.0 - P1L.3 output edge characteristic: sharp edge mode
186 1 /// P1L.4 - P1L.7 output edge characteristic: sharp edge mode
187 1
188 1 P1L = 0x0000; // load data register
189 1 ALTSEL0P1L = 0x0000; // load alternate output function select
190 1 // register 0
191 1 POCON1L = 0x0000; // load output control register
192 1 DP1L = 0x00FF; // load direction register
193 1
194 1 /// -----------------------------------------------------------------------
195 1 /// Configuration of Port P3:
196 1 /// -----------------------------------------------------------------------
197 1 /// - no pin of port P3 is used
198 1
199 1 ODP3 = 0x0000; // load open-drain register
200 1 P3 = 0x0000; // load data register
201 1 ALTSEL0P3 = 0x0000; // load alternate output function select
202 1 // register 0
203 1 ALTSEL1P3 = 0x0000; // load alternate output function select
204 1 // register 1
205 1 POCON3 = 0x0000; // load output control register
206 1 DP3 = 0x0000; // load direction register
207 1
208 1 /// -----------------------------------------------------------------------
209 1 /// Configuration of Port P4:
210 1 /// -----------------------------------------------------------------------
211 1 /// P4.0 is used as alternate input for the Port Pin (A16)
212 1 /// P4.1 is used as alternate input for the Port Pin (A17)
213 1 /// P4.2 is used as alternate input for the Chip select (CS1_n)
214 1 /// P4.3 is used as alternate input for the Chip select (CS0_n)
215 1
216 1 /// P4.0 - P4.7 threshold type: TTL input
217 1
218 1 /// P4.0 - P4.3 output driver characteristic: strong driver
219 1 /// P4.4 - P4.7 output driver characteristic: strong driver
220 1
221 1 /// P4.0 - P4.3 output edge characteristic: sharp edge mode
222 1 /// P4.4 - P4.7 output edge characteristic: sharp edge mode
223 1
224 1 ODP4 = 0x0000; // load open-drain register
225 1 P4 = 0x0000; // load data register
226 1 ALTSEL0P4 = 0x0000; // load alternate output function select
227 1 // register 0
228 1 ALTSEL1P4 = 0x0000; // load alternate output function select
229 1 // register 1
230 1 POCON4 = 0x0000; // load output control register
231 1 DP4 = 0x0000; // load direction register
232 1
233 1 /// -----------------------------------------------------------------------
234 1 /// Configuration of Port P5:
235 1 /// -----------------------------------------------------------------------
236 1 /// - no pin of port P5 is used
237 1
238 1 P5 = 0x0000; // load data register
239 1
240 1 /// -----------------------------------------------------------------------
241 1 /// Configuration of Port P9:
C166 COMPILER V6.08, IO 09/12/2008 14:54:07 PAGE 5
242 1 /// -----------------------------------------------------------------------
243 1 /// - no pin of port P9 is used
244 1
245 1 ODP9 = 0x0000; // load open-drain register
246 1 P9 = 0x0000; // load data register
247 1 ALTSEL0P9 = 0x0000; // load alternate output function select
248 1 // register 0
249 1 ALTSEL1P9 = 0x0000; // load alternate output function select
250 1 // register 1
251 1 POCON9 = 0x0000; // load output control register
252 1 DP9 = 0x0000; // load direction register
253 1
254 1 /// -----------------------------------------------------------------------
255 1 /// Configuration of Port P20:
256 1 /// -----------------------------------------------------------------------
257 1 /// - no pin of port P20 is used
258 1
259 1 P20 = 0x0000; // load data register
260 1 POCON20 = 0x0000; // load output control register
261 1 DP20 = 0x0000; // load direction register
262 1
263 1
264 1 // USER CODE BEGIN (IO_Function,3)
265 1
266 1 // USER CODE END
267 1
268 1 } // End of function IO_vInit
269
270
271
272
273 // USER CODE BEGIN (IO_General,10)
274
275 // USER CODE END
276
MODULE INFORMATION: INITIALIZED UNINITIALIZED
CODE SIZE = 170 --------
NEAR-CONST SIZE = -------- --------
FAR-CONST SIZE = -------- --------
HUGE-CONST SIZE = -------- --------
XHUGE-CONST SIZE = -------- --------
NEAR-DATA SIZE = -------- --------
FAR-DATA SIZE = -------- --------
XHUGE-DATA SIZE = -------- --------
IDATA-DATA SIZE = -------- --------
SDATA-DATA SIZE = -------- --------
BDATA-DATA SIZE = -------- --------
HUGE-DATA SIZE = -------- --------
BIT SIZE = -------- --------
INIT'L SIZE = -------- --------
END OF MODULE INFORMATION.
C166 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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