main.h

英飞凌C166之XC164CS的IO读写操作程序

//****************************************************************************
// @Module        Project Settings
// @Filename      MAIN.H
// @Project       GPIO.dav
//----------------------------------------------------------------------------
// @Controller    Infineon XC164CS-16F20
//
// @Compiler      Keil
//
// @Codegenerator 2.8
//
// @Description   This file contains all function prototypes and macros for 
//                the MAIN module.
//
//----------------------------------------------------------------------------
// @Date          2007-7-13 15:36:20
//
//****************************************************************************

// USER CODE BEGIN (MAIN_Header,1)

// USER CODE END



#ifndef _MAIN_H_
#define _MAIN_H_

//****************************************************************************
// @Project Includes
//****************************************************************************

// USER CODE BEGIN (MAIN_Header,2)

// USER CODE END


//****************************************************************************
// @Macros
//****************************************************************************

// USER CODE BEGIN (MAIN_Header,3)

// USER CODE END


//****************************************************************************
// @Defines
//****************************************************************************
#define KEIL

// USER CODE BEGIN (MAIN_Header,4)

// USER CODE END


//****************************************************************************
// @Declaration of SFRs
//****************************************************************************


// The source and destination pointers SRCPx and DSTPx
#define SRCP0                  (*((uword volatile *) 0xEC40))
#define DSTP0                  (*((uword volatile *) 0xEC42))
#define SRCP1                  (*((uword volatile *) 0xEC44))
#define DSTP1                  (*((uword volatile *) 0xEC46))
#define SRCP2                  (*((uword volatile *) 0xEC48))
#define DSTP2                  (*((uword volatile *) 0xEC4A))
#define SRCP3                  (*((uword volatile *) 0xEC4C))
#define DSTP3                  (*((uword volatile *) 0xEC4E))
#define SRCP4                  (*((uword volatile *) 0xEC50))
#define DSTP4                  (*((uword volatile *) 0xEC52))
#define SRCP5                  (*((uword volatile *) 0xEC54))
#define DSTP5                  (*((uword volatile *) 0xEC56))
#define SRCP6                  (*((uword volatile *) 0xEC58))
#define DSTP6                  (*((uword volatile *) 0xEC5A))
#define SRCP7                  (*((uword volatile *) 0xEC5C))
#define DSTP7                  (*((uword volatile *) 0xEC5E))

// ADC End of Conversion Interrupt Control Register
#define ADC_CIC                (*((uword volatile *) 0xFF98))
#define ADC_CIC_GPX                      ((T_Reg16 *) 0xFF98)->bit8
#define ADC_CIC_IE                       ((T_Reg16 *) 0xFF98)->bit6
#define ADC_CIC_IR                       ((T_Reg16 *) 0xFF98)->bit7

// A/D Converter Control Register
#define ADC_CON                (*((uword volatile *) 0xFFA0))
#define ADC_CON_ADBSY                    ((T_Reg16 *) 0xFFA0)->bit8
#define ADC_CON_ADCIN                    ((T_Reg16 *) 0xFFA0)->bit10
#define ADC_CON_ADCRQ                    ((T_Reg16 *) 0xFFA0)->bit11
#define ADC_CON_ADST                     ((T_Reg16 *) 0xFFA0)->bit7
#define ADC_CON_ADWR                     ((T_Reg16 *) 0xFFA0)->bit9

// A/D Converter Control Register 1
#define ADC_CON1               (*((uword volatile *) 0xFFA6))
#define ADC_CON1_CAL                      ((T_Reg16 *) 0xFFA6)->bit13
#define ADC_CON1_ICST                     ((T_Reg16 *) 0xFFA6)->bit15
#define ADC_CON1_RES                      ((T_Reg16 *) 0xFFA6)->bit12
#define ADC_CON1_SAMPLE                   ((T_Reg16 *) 0xFFA6)->bit14

// A/D Converter Control Register 0
#define ADC_CTR0               (*((uword volatile *) 0xFFBE))
#define ADC_CTR0_0                        ((T_Reg16 *) 0xFFBE)->bit4
#define ADC_CTR0_ADBSY                    ((T_Reg16 *) 0xFFBE)->bit8
#define ADC_CTR0_ADCIN                    ((T_Reg16 *) 0xFFBE)->bit10
#define ADC_CTR0_ADCRQ                    ((T_Reg16 *) 0xFFBE)->bit11
#define ADC_CTR0_ADST                     ((T_Reg16 *) 0xFFBE)->bit7
#define ADC_CTR0_ADWR                     ((T_Reg16 *) 0xFFBE)->bit9
#define ADC_CTR0_MD                       ((T_Reg16 *) 0xFFBE)->bit15
#define ADC_CTR0_SMPL                     ((T_Reg16 *) 0xFFBE)->bit14

// A/D Converter Control Register 2
#define ADC_CTR2               (*((uword volatile *) 0xF09C))

// A/D Converter Injection Control Register 2
#define ADC_CTR2IN             (*((uword volatile *) 0xF09E))

// A/D Converter Result Register
#define ADC_DAT                (*((uword volatile *) 0xFEA0))

// A/D Converter Result Register 2
#define ADC_DAT2               (*((uword volatile *) 0xF0A0))

// ADC Overrun Error Control Register
#define ADC_EIC                (*((uword volatile *) 0xFF9A))
#define ADC_EIC_GPX                      ((T_Reg16 *) 0xFF9A)->bit8
#define ADC_EIC_IE                       ((T_Reg16 *) 0xFF9A)->bit6
#define ADC_EIC_IR                       ((T_Reg16 *) 0xFF9A)->bit7

// CS1 Address Range and Size Selection Register
#define ADDRSEL1               (*((uword volatile *) 0xEE1E))

// CS2 Address Range and Size Selection Register
#define ADDRSEL2               (*((uword volatile *) 0xEE26))

// CS3 Address Range and Size Selection Register
#define ADDRSEL3               (*((uword volatile *) 0xEE2E))

// CS4 Address Range and Size Selection Register
#define ADDRSEL4               (*((uword volatile *) 0xEE36))

// CS5 Address Range and Size Selection Register
#define ADDRSEL5               (*((uword volatile *) 0xEE3E))

// CS6 Address Range and Size Selection Register
#define ADDRSEL6               (*((uword volatile *) 0xEE46))

// CS7 Address Range and Size Selection Register
#define ADDRSEL7               (*((uword volatile *) 0xEE4E))

// Alternate I/O Source 0 Port P1H
#define ALTSEL0P1H             (*((uword volatile *) 0xF120))
#define ALTSEL0P1H_P0                       ((T_Reg16 *) 0xF120)->bit0
#define ALTSEL0P1H_P1                       ((T_Reg16 *) 0xF120)->bit1
#define ALTSEL0P1H_P2                       ((T_Reg16 *) 0xF120)->bit2
#define ALTSEL0P1H_P3                       ((T_Reg16 *) 0xF120)->bit3
#define ALTSEL0P1H_P4                       ((T_Reg16 *) 0xF120)->bit4
#define ALTSEL0P1H_P5                       ((T_Reg16 *) 0xF120)->bit5
#define ALTSEL0P1H_P6                       ((T_Reg16 *) 0xF120)->bit6
#define ALTSEL0P1H_P7                       ((T_Reg16 *) 0xF120)->bit7

// P1L Alternate Select Register 0
#define ALTSEL0P1L             (*((uword volatile *) 0xF130))
#define ALTSEL0P1L_P0                       ((T_Reg16 *) 0xF130)->bit0
#define ALTSEL0P1L_P1                       ((T_Reg16 *) 0xF130)->bit1
#define ALTSEL0P1L_P2                       ((T_Reg16 *) 0xF130)->bit2
#define ALTSEL0P1L_P3                       ((T_Reg16 *) 0xF130)->bit3
#define ALTSEL0P1L_P4                       ((T_Reg16 *) 0xF130)->bit4
#define ALTSEL0P1L_P5                       ((T_Reg16 *) 0xF130)->bit5
#define ALTSEL0P1L_P6                       ((T_Reg16 *) 0xF130)->bit6
#define ALTSEL0P1L_P7                       ((T_Reg16 *) 0xF130)->bit7

// Alternate I/O Source Port 3 Selection
#define ALTSEL0P3              (*((uword volatile *) 0xF126))
#define ALTSEL0P3_P1                       ((T_Reg16 *) 0xF126)->bit1
#define ALTSEL0P3_P10                      ((T_Reg16 *) 0xF126)->bit10
#define ALTSEL0P3_P11                      ((T_Reg16 *) 0xF126)->bit11
#define ALTSEL0P3_P13                      ((T_Reg16 *) 0xF126)->bit13
#define ALTSEL0P3_P3                       ((T_Reg16 *) 0xF126)->bit3
#define ALTSEL0P3_P5                       ((T_Reg16 *) 0xF126)->bit5
#define ALTSEL0P3_P8                       ((T_Reg16 *) 0xF126)->bit8
#define ALTSEL0P3_P9                       ((T_Reg16 *) 0xF126)->bit9

// Alternate I/O Source 0 Port P4
#define ALTSEL0P4              (*((uword volatile *) 0xF12A))
#define ALTSEL0P4_P6                       ((T_Reg16 *) 0xF12A)->bit6
#define ALTSEL0P4_P7                       ((T_Reg16 *) 0xF12A)->bit7

// Alternate I/O Source 0 Port P9
#define ALTSEL0P9              (*((uword volatile *) 0xF138))
#define ALTSEL0P9_P0                       ((T_Reg16 *) 0xF138)->bit0
#define ALTSEL0P9_P1                       ((T_Reg16 *) 0xF138)->bit1
#define ALTSEL0P9_P2                       ((T_Reg16 *) 0xF138)->bit2
#define ALTSEL0P9_P3                       ((T_Reg16 *) 0xF138)->bit3
#define ALTSEL0P9_P4                       ((T_Reg16 *) 0xF138)->bit4
#define ALTSEL0P9_P5                       ((T_Reg16 *) 0xF138)->bit5

// Alternate I/O Source 1 Port P3
#define ALTSEL1P3              (*((uword volatile *) 0xF128))
#define ALTSEL1P3_P1                       ((T_Reg16 *) 0xF128)->bit1

// Alternate I/O Source 1 Port P4
#define ALTSEL1P4              (*((uword volatile *) 0xF136))
#define ALTSEL1P4_P7                       ((T_Reg16 *) 0xF136)->bit7

// Alternate I/O Source 1 Port P9
#define ALTSEL1P9              (*((uword volatile *) 0xF13A))
#define ALTSEL1P9_P0                       ((T_Reg16 *) 0xF13A)->bit0
#define ALTSEL1P9_P1                       ((T_Reg16 *) 0xF13A)->bit1
#define ALTSEL1P9_P2                       ((T_Reg16 *) 0xF13A)->bit2
#define ALTSEL1P9_P3                       ((T_Reg16 *) 0xF13A)->bit3
#define ALTSEL1P9_P4                       ((T_Reg16 *) 0xF13A)->bit4
#define ALTSEL1P9_P5                       ((T_Reg16 *) 0xF13A)->bit5

// ASC0 Autobaud Control Register
#define ASC0_ABCON             (*((uword volatile *) 0xF1B8))
#define ASC0_ABCON_ABDETEN                  ((T_Reg16 *) 0xF1B8)->bit3
#define ASC0_ABCON_ABEN                     ((T_Reg16 *) 0xF1B8)->bit0
#define ASC0_ABCON_ABSTEN                   ((T_Reg16 *) 0xF1B8)->bit2
#define ASC0_ABCON_AUREN                    ((T_Reg16 *) 0xF1B8)->bit1
#define ASC0_ABCON_FCDETEN                  ((T_Reg16 *) 0xF1B8)->bit4
#define ASC0_ABCON_RXINV                    ((T_Reg16 *) 0xF1B8)->bit11
#define ASC0_ABCON_TXINV                    ((T_Reg16 *) 0xF1B8)->bit10

// ASC0 Autobaud Interrupt Control Register
#define ASC0_ABIC              (*((uword volatile *) 0xF15C))
#define ASC0_ABIC_GPX                      ((T_Reg16 *) 0xF15C)->bit8
#define ASC0_ABIC_IE                       ((T_Reg16 *) 0xF15C)->bit6
#define ASC0_ABIC_IR                       ((T_Reg16 *) 0xF15C)->bit7

// ASC0 Autobaud Status Register
#define ASC0_ABSTAT            (*((uword volatile *) 0xF0B8))
#define ASC0_ABSTAT_DETWAIT                  ((T_Reg16 *) 0xF0B8)->bit4
#define ASC0_ABSTAT_FCCDET                   ((T_Reg16 *) 0xF0B8)->bit1
#define ASC0_ABSTAT_FCSDET                   ((T_Reg16 *) 0xF0B8)->bit0
#define ASC0_ABSTAT_SCCDET                   ((T_Reg16 *) 0xF0B8)->bit3
#define ASC0_ABSTAT_SCSDET                   ((T_Reg16 *) 0xF0B8)->bit2

// Serial Channel 0 Baud Rate Generator Reload Register
#define ASC0_BG                (*((uword volatile *) 0xFEB4))

// Serial Channel 0 Control Register
#define ASC0_CON               (*((uword volatile *) 0xFFB0))
#define ASC0_CON_BRS                      ((T_Reg16 *) 0xFFB0)->bit13
#define ASC0_CON_FDE                      ((T_Reg16 *) 0xFFB0)->bit11
#define ASC0_CON_FE                       ((T_Reg16 *) 0xFFB0)->bit9
#define ASC0_CON_FEN                      ((T_Reg16 *) 0xFFB0)->bit6
#define ASC0_CON_LB                       ((T_Reg16 *) 0xFFB0)->bit14
#define ASC0_CON_ODD                      ((T_Reg16 *) 0xFFB0)->bit12
#define ASC0_CON_OE                       ((T_Reg16 *) 0xFFB0)->bit10
#define ASC0_CON_OEN                      ((T_Reg16 *) 0xFFB0)->bit7
#define ASC0_CON_PE                       ((T_Reg16 *) 0xFFB0)->bit8
#define ASC0_CON_PEN_RXDI                 ((T_Reg16 *) 0xFFB0)->bit5
#define ASC0_CON_R                        ((T_Reg16 *) 0xFFB0)->bit15
#define ASC0_CON_REN                      ((T_Reg16 *) 0xFFB0)->bit4
#define ASC0_CON_STP                      ((T_Reg16 *) 0xFFB0)->bit3

// ASC0 Error Interrupt Control Register
#define ASC0_EIC               (*((uword volatile *) 0xFF70))
#define ASC0_EIC_GPX                      ((T_Reg16 *) 0xFF70)->bit8
#define ASC0_EIC_IE                       ((T_Reg16 *) 0xFF70)->bit6
#define ASC0_EIC_IR                       ((T_Reg16 *) 0xFF70)->bit7

// Fractional Divider Register
#define ASC0_FDV               (*((uword volatile *) 0xFEB6))

// FIFO Status Register
#define ASC0_FSTAT             (*((uword volatile *) 0xF0BA))

// ASC0 IrDA Pulse Mode and Width Reg.
#define ASC0_PMW               (*((uword volatile *) 0xFEAA))

// Serial Channel 0 Receiver Buffer Register (RO)
#define ASC0_RBUF              (*((uword volatile *) 0xFEB2))

// ASC0 Receive Interrupt Control Register
#define ASC0_RIC               (*((uword volatile *) 0xFF6E))
#define ASC0_RIC_GPX                      ((T_Reg16 *) 0xFF6E)->bit8
#define ASC0_RIC_IE                       ((T_Reg16 *) 0xFF6E)->bit6
#define ASC0_RIC_IR                       ((T_Reg16 *) 0xFF6E)->bit7

// Receive FIFO Control Register
#define ASC0_RXFCON            (*((uword volatile *) 0xF0C6))
#define ASC0_RXFCON_RXFEN                    ((T_Reg16 *) 0xF0C6)->bit0
#define ASC0_RXFCON_RXFFLU                   ((T_Reg16 *) 0xF0C6)->bit1
#define ASC0_RXFCON_RXTMEN                   ((T_Reg16 *) 0xF0C6)->bit2

// ASC0 Transmit Buffer Interrupt Control Register
#define ASC0_TBIC              (*((uword volatile *) 0xF19C))
#define ASC0_TBIC_GPX                      ((T_Reg16 *) 0xF19C)->bit8