📄 start_v2.lst
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641 ;
642 ; <o>PHD1: Phase D clock cycles (TCONCS1.5) <0-1>
0000 643 _PHD1 EQU 0 ; 0 = 0 clock cycles
644 ; 1 = 1 clock cycle
645 ;
646 ; <o> PHE1: Phase E clock cycles (TCONCS1.6 .. TCONCS1.10) <1-32> <#-1>
0008 647 _PHE1 EQU 8 ; 0 = 1 clock cycle
A166 MACRO ASSEMBLER START_V2 08/30/2007 18:29:22 PAGE 11
648 ; : = :
649 ; 31 = 32 clock cycles
650 ;
651 ; <o>RDPHF1: Phase F read clock cycles (TCONCS1.11 .. TCONCS1.12) <0-3>
0000 652 _RDPHF1 EQU 0 ; 0 = 0 clock cycles
653 ; : = :
654 ; 3 = 3 clock cycles
655 ;
656 ; <o>WRPHF1: Phase F write clock cycles (TCONCS1.13 .. TCONCS1.14) <0-3>
0003 657 _WRPHF1 EQU 3 ; 0 = 0 clock cycles
658 ; : = :
659 ; 3 = 3 clock cycles
660 ;</h> </e>
661 ;
662 ;<e>Configure External Bus Behaviour for CS2 Area
663 ; =============================================
664 ;
665 ; --- Set CONFIG_CS2 = 1 to initialize the ADDRSEL2/FCONCS2/TCONCS2 registers
666 $SET (CONFIG_CS2 = 0)
667 ;
668 ; <h>Definitions for Address Select register ADDRSEL2
669 ; ===================================================
670 ; <o> CS2 Start Address <0x0-0xFFFFFF:0x1000>
00200000 671 _ADDR2 EQU 0x200000 ; Set CS2# Start Address (default 100000H)
672
673 ; <o> CS2 Size in KB
674 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
675 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
676 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
00100000 677 _SIZE2 EQU 1024*KB ; Set CS2# Size (default 1024*KB = 1*MB)
678 ; possible values for _SIZE2 are:
679 ; 4*KB (gives RGSZ2 = 0)
680 ; 8*KB (gives RGSZ2 = 1)
681 ; 16*KB (gives RGSZ2 = 2)
682 ; 32*KB (gives RGSZ2 = 3)
683 ; 64*KB (gives RGSZ2 = 4)
684 ; 128*KB (gives RGSZ2 = 5)
685 ; 256*KB (gives RGSZ2 = 6)
686 ; 512*KB (gives RGSZ2 = 7)
687 ; 1024*KB or 1*MB (gives RGSZ2 = 8)
688 ; 2048*KB or 2*MB (gives RGSZ2 = 9)
689 ; 4096*KB or 4*MB (gives RGSZ2 = 10)
690 ; 8192*KB or 8*MB (gives RGSZ2 = 11)
691 ; (RGSZ2 = 12 .. 15 reserved)
692 ;</h>
693 ;
694 ; <h>Definitions for Function Configuration Register FCONCS2
695 ; =======================================================
696 ;
697 ; <q> ENCS2: Enable Chip Select (FCONCS2.0)
0001 698 _ENCS2 EQU 1 ; 0 = Chip Select 0 disabled
699 ; 1 = Chip Select 0 enabled
700 ;
701 ; <q> RDYEN2: Ready Enable (FCONCS2.1)
0000 702 _RDYEN2 EQU 0 ; 0 = Access time controlled by TCONCS2.PHE1
703 ; 1 = Access time cont. by TCONCS2.PHE1 and READY signal
704 ;
705 ; <o> RDYMOD2: Ready Mode (FCONCS2.2)
706 ; <0=> Asynchronous <1=> Synchronous
0000 707 _RDYMOD2 EQU 0 ; 0 = Asynchronous READY
708 ; 1 = Synchronous READY
709 ;
710 ; <o> BTYP2: Bus Type Selection (FCONCS2.4 .. FCONCS2.5)
711 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
712 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0002 713 _BTYP2 EQU 2 ; 0 = 8 bit Demultiplexed bus
A166 MACRO ASSEMBLER START_V2 08/30/2007 18:29:22 PAGE 12
714 ; 1 = 8 bit Multiplexed bus
715 ; 2 = 16 bit Demultiplexed bus
716 ; 3 = 16 bit Multiplexed bus
717 ;</h>
718 ;
719 ; <h>TCONCS2: Definitions for the Timing Configuration register
720 ; ==========================================================
721 ;
722 ; <o>PHA2: Phase A clock cycle (TCONCS2.0 .. TCONCS2.1) <0-3>
0000 723 _PHA2 EQU 0 ; 0 = 0 clock cycles
724 ; : = :
725 ; 3 = 3 clock cycles
726 ;
727 ; <o>PHB2: Phase B clock cycle (TCONCS2.2) <1-2> <#-1>
0000 728 _PHB2 EQU 0 ; 0 = 1 clock cycle
729 ; 1 = 2 clock cycles
730 ;
731 ; <o>PHC2: Phase C clock cycle (TCONCS2.3 .. TCONCS2.4) <0-3>
0000 732 _PHC2 EQU 0 ; 0 = 0 clock cycles
733 ; : = :
734 ; 3 = 3 clock cycles
735 ;
736 ; <o>PHD2: Phase D clock cycle (TCONCS2.5) <0-1>
0000 737 _PHD2 EQU 0 ; 0 = 0 clock cycles
738 ; 1 = 1 clock cycle
739 ;
740 ; <o> PHE2: Phase E clock cycle (TCONCS2.6 .. TCONCS2.10) <1-32> <#-1>
0008 741 _PHE2 EQU 8 ; 0 = 1 clock cycle
742 ; : = :
743 ; 31 = 32 clock cycles
744 ;
745 ; <o>RDPHF2: Phase F read clock cycle (TCONCS2.11 .. TCONCS2.12) <0-3>
0000 746 _RDPHF2 EQU 0 ; 0 = 0 clock cycles
747 ; : = :
748 ; 3 = 3 clock cycles
749 ;
750 ; <o>WRPHF2: Phase F write clock cycle (TCONCS2.13 .. TCONCS2.14) <0-3>
0003 751 _WRPHF2 EQU 3 ; 0 = 0 clock cycles
752 ; : = :
753 ; 3 = 3 clock cycles
754 ;</h> </e>
755 ;
756 ;<e>Configure External Bus Behaviour for CS3 Area
757 ; =============================================
758 ;
759 ; --- Set CONFIG_CS3 = 1 to initialize the ADDRSEL3/FCONCS3/TCONCS3 registers
760 $SET (CONFIG_CS3 = 0)
761 ;
762 ; <h>Definitions for Address Select register ADDRSEL3
763 ; ===================================================
764 ; <o> CS3 Start Address <0x0-0xFFFFFF:0x1000>
00300000 765 _ADDR3 EQU 0x300000 ; Set CS3# Start Address (default 100000H)
766
767 ; <o> CS2 Size in KB
768 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
769 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
770 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
00100000 771 _SIZE3 EQU 1024*KB ; Set CS3# Size (default 1024*KB = 1*MB)
772 ; possible values for _SIZE3 are:
773 ; 4*KB (gives RGSZ3 = 0)
774 ; 8*KB (gives RGSZ3 = 1)
775 ; 16*KB (gives RGSZ3 = 2)
776 ; 32*KB (gives RGSZ3 = 3)
777 ; 64*KB (gives RGSZ3 = 4)
778 ; 128*KB (gives RGSZ3 = 5)
779 ; 256*KB (gives RGSZ3 = 6)
A166 MACRO ASSEMBLER START_V2 08/30/2007 18:29:22 PAGE 13
780 ; 512*KB (gives RGSZ3 = 7)
781 ; 1024*KB or 1*MB (gives RGSZ3 = 8)
782 ; 2048*KB or 2*MB (gives RGSZ3 = 9)
783 ; 4096*KB or 4*MB (gives RGSZ3 = 10)
784 ; 8192*KB or 8*MB (gives RGSZ3 = 11)
785 ; (RGSZ3 = 12 .. 15 reserved)
786 ;</h>
787 ;
788 ; <h>Definitions for Function Configuration Register FCONCS3
789 ; =======================================================
790 ;
791 ; <q> ENCS3: Enable Chip Select (FCONCS3.0)
0001 792 _ENCS3 EQU 1 ; 0 = Chip Select 0 disabled
793 ; 1 = Chip Select 0 enabled
794 ;
795 ; <q> RDYEN3: Ready Enable (FCONCS3.1)
0000 796 _RDYEN3 EQU 0 ; 0 = Access time controlled by TCONCS3.PHE1
797 ; 1 = Access time cont. by TCONCS3.PHE1 and READY signal
798 ;
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