📄 start_v2.lst
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477 ; 1 = Pin A15 disabled, A14-1 enabled
478 ; 2 = Pin A15-A14 disabled, A13-1 enabled
479 ; ...
480 ; 15 = Pins A15-A1 disabled
481 ;
482 ; <q> A0PDIS: Address Bit 0 Pin Disable (EBCMOD1.4)
0000 483 _A0PDIS EQU 0 ; 0 = Address bus pin 0 of PORT1 enabled
484 ; 1 = Address bus pin 0 of PORT1 enabled
485 ;
486 ; <q> ALPDIS: Address Low Pins Disable (EBCMOD1.5)
0000 487 _ALPDIS EQU 0 ; 0 = Address bus pin 7-0 generally enabled
488 ; 1 = Address bus pin 7-0 of PORT1 disabled
489 ;
490 ; <q> DHPDIS: Data High Port Pins Disable (EBCMOD1.6)
0000 491 _DPPDIS EQU 0 ; 0 = Data bus pins 15-8 of PORT0 enabled
492 ; 1 = Data bus pins 15-8 disabled (used as GPIO)
493 ;
494 ; <q> WRPDIS: WR/WRL Pin Disable (EBCMOD1.7)
0000 495 _WRPDIS EQU 0 ; 0 = WR/WRL pin of Port P20 enabled
496 ; 1 = WR/WRL pin of Port P20 disabled
497 ;
498 ;</h></e>
499 ;
500 ; <e>Configure External Bus Behaviour for CS0 area
501 ; ================================================
502 ;
503 ; --- Set CONFIG_CS0 = 1 to initialize the FCONCS0/TCONCS0 registers
504 $SET (CONFIG_CS0 = 1)
505 ;
506 ; <h>Definitions for Function Configuration Register FCONCS0
507 ; =======================================================
508 ;
509 ; <q> ENCS0: Enable Chip Select (FCONCS0.0)
0001 510 _ENCS0 EQU 1 ; 0 = Chip Select 0 disabled
511 ; 1 = Chip Select 0 enabled
512 ;
513 ; <q> RDYEN0: Ready Enable (FCONCS0.1)
0000 514 _RDYEN0 EQU 0 ; 0 = Access time controlled by TCONCS0.PHE0
515 ; 1 = Access time cont. by TCONCS0.PHE0 and READY signal
A166 MACRO ASSEMBLER START_V2 08/30/2007 18:29:22 PAGE 9
516 ;
517 ; <o> RDYMOD0: Ready Mode (FCONCS0.2)
518 ; <0=> Asynchronous <1=> Synchronous
0000 519 _RDYMOD0 EQU 0 ; 0 = Asynchronous READY
520 ; 1 = Synchronous READY
521 ;
522 ; <o> BTYP0: Bus Type Selection (FCONCS0.4 .. FCONCS0.5)
523 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
524 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0003 525 _BTYP0 EQU 3 ; 0 = 8 bit Demultiplexed bus
526 ; 1 = 8 bit Multiplexed bus
527 ; 2 = 16 bit Demultiplexed bus
528 ; 3 = 16 bit Multiplexed bus
529 ; </h>
530 ;
531 ; <h> TCONCS0: Definitions for the Timing Configuration register
532 ; ==========================================================
533 ;
534 ; <o> PHA0: Phase A clock cycles (TCONCS0.0 .. TCONCS0.1) <0-3>
0003 535 _PHA0 EQU 3 ; 0 = 0 clock cycles
536 ; : = :
537 ; 3 = 3 clock cycles
538 ;
539 ; <o> PHB0: Phase B clock cycles (TCONCS0.2) <1-2> <#-1>
0001 540 _PHB0 EQU 1 ; 0 = 1 clock cycle
541 ; 1 = 2 clock cycles
542 ;
543 ; <o> PHC0: Phase C clock cycles (TCONCS0.3 .. TCONCS0.4) <0-3>
0009 544 _PHC0 EQU 9 ; 0 = 0 clock cycles
545 ; : = :
546 ; 3 = 3 clock cycles
547 ;
548 ; <o> PHD0: Phase D clock cycle (TCONCS0.5) <0-1>
0001 549 _PHD0 EQU 1 ; 0 = 0 clock cycles
550 ; 1 = 1 clock cycle
551 ;
552 ; <o> PHE0: Phase E clock cycles (TCONCS0.6 .. TCONCS0.10) <1-32> <#-1>
0003 553 _PHE0 EQU 3 ; 0 = 1 clock cycle
554 ; : = :
555 ; 31 = 32 clock cycles
556 ;
557 ; <o> RDPHF0: Phase F read clock cycles (TCONCS0.11 .. TCONCS0.12) <0-3>
0000 558 _RDPHF0 EQU 0 ; 0 = 0 clock cycles
559 ; : = :
560 ; 3 = 3 clock cycles
561 ;
562 ; <o> WRPHF0: Phase F write clock cycles (TCONCS0.13 .. TCONCS0.14) <0-3>
0003 563 _WRPHF0 EQU 3 ; 0 = 0 clock cycles
564 ; : = :
565 ; 3 = 3 clock cycles
566 ;</h> </e>
567 ;
568 ;<e>Configure External Bus Behaviour for CS1 Area
569 ; =============================================
570 ;
571 ; --- Set CONFIG_CS1 = 1 to initialize the ADDRSEL1/FCONCS1/TCONCS1 registers
572 $SET (CONFIG_CS1 = 0)
573 ;
574 ; <h>Definitions for Address Select register ADDRSEL1
575 ; ===================================================
576 ; <o> CS1 Start Address <0x0-0xFFFFFF:0x1000>
00100000 577 _ADDR1 EQU 0x100000 ; Set CS1# Start Address (default 100000H)
578
579 ; <o> CS1 Size in KB
580 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
581 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
A166 MACRO ASSEMBLER START_V2 08/30/2007 18:29:22 PAGE 10
582 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
00100000 583 _SIZE1 EQU 1024*KB ; Set CS1# Size (default 1024*KB = 1*MB)
584 ; possible values for _SIZE1 are:
585 ; 4*KB (gives RGSZ1 = 0)
586 ; 8*KB (gives RGSZ1 = 1)
587 ; 16*KB (gives RGSZ1 = 2)
588 ; 32*KB (gives RGSZ1 = 3)
589 ; 64*KB (gives RGSZ1 = 4)
590 ; 128*KB (gives RGSZ1 = 5)
591 ; 256*KB (gives RGSZ1 = 6)
592 ; 512*KB (gives RGSZ1 = 7)
593 ; 1024*KB or 1*MB (gives RGSZ1 = 8)
594 ; 2048*KB or 2*MB (gives RGSZ1 = 9)
595 ; 4096*KB or 4*MB (gives RGSZ1 = 10)
596 ; 8192*KB or 8*MB (gives RGSZ1 = 11)
597 ; (RGSZ1 = 12 .. 15 reserved)
598 ;</h>
599 ;
600 ; <h>Definitions for Function Configuration Register FCONCS1
601 ; =======================================================
602 ;
603 ; <q> ENCS1: Enable Chip Select (FCONCS1.0)
0001 604 _ENCS1 EQU 1 ; 0 = Chip Select 0 disabled
605 ; 1 = Chip Select 0 enabled
606 ;
607 ; <q> RDYEN1: Ready Enable (FCONCS1.1)
0000 608 _RDYEN1 EQU 0 ; 0 = Access time controlled by TCONCS1.PHE1
609 ; 1 = Access time cont. by TCONCS1.PHE1 and READY signal
610 ;
611 ; <o> RDYMOD1: Ready Mode (FCONCS1.2)
612 ; <0=> Asynchronous <1=> Synchronous
0000 613 _RDYMOD1 EQU 0 ; 0 = Asynchronous READY
614 ; 1 = Synchronous READY
615 ;
616 ; <o> BTYP1: Bus Type Selection (FCONCS1.4 .. FCONCS1.5)
617 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
618 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0002 619 _BTYP1 EQU 2 ; 0 = 8 bit Demultiplexed bus
620 ; 1 = 8 bit Multiplexed bus
621 ; 2 = 16 bit Demultiplexed bus
622 ; 3 = 16 bit Multiplexed bus
623 ;</h>
624 ;
625 ; <h>TCONCS1: Definitions for the Timing Configuration register
626 ; ==========================================================
627 ;
628 ; <o>PHA1: Phase A clock cycles (TCONCS1.0 .. TCONCS1.1) <0-3>
0000 629 _PHA1 EQU 0 ; 0 = 0 clock cycles
630 ; : = :
631 ; 3 = 3 clock cycles
632 ;
633 ; <o>PHB1: Phase B clock cycles (TCONCS1.2) <1-2> <#-1>
0000 634 _PHB1 EQU 0 ; 0 = 1 clock cycle
635 ; 1 = 2 clock cycles
636 ;
637 ; <o>PHC1: Phase C clock cycles (TCONCS1.3 .. TCONCS1.4) <0-3>
0000 638 _PHC1 EQU 0 ; 0 = 0 clock cycles
639 ; : = :
640 ; 3 = 3 clock cycles
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