📄 start_v2.lst
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319 ; --- Set INIT_PLLCON = 0 to initilize the PLLCON register
320 $SET (INIT_PLLCON = 1)
321 ;
A166 MACRO ASSEMBLER START_V2 08/30/2007 18:29:22 PAGE 6
322 ; <o> PLLODIV: PLL Output Devider (PLLCON.0 .. PLLCON.3) <0-14>
0005 323 _PLLODIV EQU 5 ; 0 .. 14 Fpll = Fvco / (PLLODIV+1)
324 ; 15 = reserved
325 ;
326 ; <o> PLLIDIV: PLL Input Devider (PLLCON.4 .. PLLCON.5) <0-3>
327 ; <i> Fin = Fosc / (PLLIDIV+1)
0000 328 _PLLIDIV EQU 0 ; 0 .. 3 Fin = Fosc / (PLLIDIV+1)
329 ;
330 ; <o> PLLVB: PLL VCO Band Select (PLLCON.6 .. PLLCON.7)
331 ; <0=> Ouput:100-150MHz / Base:20-80MHz <1=> Ouput:150-200MHz / Base:40-130MHz
332 ; <2=> Ouput:200-250MHz / Base:60-180MHz <3=> (250...300 MHz) Reserved
0002 333 _PLLVB EQU 2 ; ValueVCO output frequency Base frequency
334 ; 0 = 100...150 MHz 20...80 MHz
335 ; 1 = 150...200 MHz 40...130 MHz
336 ; 2 = 200...250 MHz [def.] 60...180 MHz
337 ; 3 = (250...300 MHz) Reserved
338 ;
339 ; <o> PLLMUL: PLL Multiplication Factor (PLLCON.8 .. PLLCON.12) <6-31>
340 ; <i> Fvco = Fin * (PLLMUL+1)
0019 341 _PLLMUL EQU 25 ; 7 .. 31 Fvco = Fin * (PLLMUL+1)
342 ; 0 .. 6 = reserved
343 ;
344 ; <o> PLLCTRL: PLL Operation Control (PLLCON.13 .. PLLCON.14)
345 ; <0=> Bypass PLL clock mult., the VCO is off <1=> Bypass PLL clock mult., the VCO i
s running
346 ; <2=> VCO clock used, input clock switched off <3=> VCO clock used, input clock conne
cted
0003 347 _PLLCTRL EQU 3 ; 0 = Bypass PLL clock mult., the VCO is off
348 ; 1 = Bypass PLL clock mult., the VCO is running
349 ; 2 = VCO clock used, input clock switched off
350 ; 3 = VCO clock used, input clock connected
351 ;
352 ; <o> PLLWRI: PLLCON Write Ignore Flag (PLLCON.15)
353 ; <0=> Register PLLCON may be written <1=> Write cycles to register PLLCON are ignore
d
0000 354 _PLLWRI EQU 0 ; 0 = Register PLLCON may be written
355 ; 1 = Write cycles to register PLLCON are ignored
356 ;</e>
357 ;
358 ; <e> Definitions for Watchdog Timer Control Register WDTCON
359 ; ======================================================
360 ;
361 ; --- Set WATCHDOG = 0 to enable the Hardware watchdog and initilize the WDTCON regist
er
362 $SET (WATCHDOG = 0) ; 0 = Disabled Hardware watchdog
363 ;
364 ; <o> WDTIN: Watchdog Timer Input Frequency Select (WDTCON.0 .. WDTCON.1)
365 ; <0=> Peripheral Frequency divided by 2 <1=> Peripheral Frequency divided by 128
366 ; <2=> Peripheral Frequency divided by 4 <3=> Peripheral Frequency divided by 256
0001 367 _WDTIN EQU 1 ; 0 = frequency f_peripheral / 2 (CPU default)
368 ; 1 = frequency f_peripheral / 128 (recommended for START_V2)
369 ; 2 = frequency f_peripheral / 4
370 ; 3 = frequency f_peripheral / 256
371 ;
372 ; <o> WDTREL: Watchdog Timer Reload Value (WDTCON8 .. WDTCON15) <0-255>
373 ; <i> High byte of WDT (counts up, overflow gives Watchdog reset)
0000 374 _WDTREL EQU 0
375 ;
376 ;</e>
377 ; <e> Definitions for Frequency Output Signal FOCON
378 ; =================================================
379 ;
380 ; INIT_FOCON: Init FOCON register
381 ; --- Set INIT_FOCON = 0 to initilize the FOCON register
382 $SET (INIT_FOCON = 1)
383 ;
A166 MACRO ASSEMBLER START_V2 08/30/2007 18:29:22 PAGE 7
384 ; <o> CLKEN: CLKOUT Enable (FOCON.7)
385 ; <0=> P3.15 is IO <1=> P3.15 is CLKOUT
0000 386 _CLKEN EQU 0 ; 0 = P3.15 is IO pin when _FOUT is 0
387 ; 1 = P3.15 outputs signal CLKOUT
388 ;
389 ; <o> FORV: Frequency Output Reload Value (FOCON.8 .. FOCON.13) <0-63>
390 ; <i> Is copied to FOCNT upon each underflow of FOCNT
0000 391 _FORV EQU 0
392 ;
393 ; <o> FOSS: Frequency Output Signal Select (FOCON.14)
394 ; <0=> Output of Toggle Latch <1=> Output of Reload Counter
0000 395 _FOSS EQU 0 ; 0 = Output of the toggle latch; 0.5 duty cycle
396 ; 1 = Output of reload counter; duty cycle depends on FORV
397 ;
398 ; <o> FOEN: Frequency Output Enable (FOCON.15)
399 ; <0=> P3.15 is IO <1=> P3.15 outputs f_OUT
0000 400 _FOEN EQU 0 ; 0 = P3.15 is IO pin when _CLKEN is 0
401 ; 1 = P3.15 outputs f_OUT when _CLKEN is 0
402 ;</e>
403 ;
404 ;<h> External Bus Configuration
405 ;
406 ; <e> Configure External Bus (EBC) Behaviour
407 ; ==========================================
408 ;
409 ; --- Set CONFIG_EBC = 0 to initialize the EBCMOD0/EBCMOD1 registers
410 $SET (CONFIG_EBC = 0) ; 0 = EBCMOD0/EBCMOD1 are set during reset according the
411 ; of configuration bus (typical Port0) values.
412 ; 1 = the following external bus configuration values
413 ; are written to EBCMOD and BUSACT0
414 ;
415 ; <h>Definitions for EBC Mode 0 register EBCMOD0
416 ; ===========================================
417 ;
418 ; <o> SAPEN: Segment Address Pins Enabled (EBCMOD0.0 .. EBCMOD0.3) <0-8>
419 ; <i> Number of active Address Lines (A16-A23)
0002 420 _SAPEN EQU 2 ; 0 = No segment address pins enabled
421 ; 1 = One (A16) segment address pin enabled
422 ; : = :
423 ; 8 = Eight (A16 .. A23) address pins enabled
424 ; 9 - 15 = reserved
425 ;
426 ; <o> CSPEN: CSx Pins Enabled (EBCMOD0.4 .. EBCMOD0.7) <0-8>
427 ; <i> Number of active ChipSelect pins
0001 428 _CSPEN EQU 1 ; 0 = No CS pins enabled
429 ; 1 = One CS (CS0) pin enabled
430 ; : = :
431 ; 8 = Eight CS (CS0 .. CS7) pins enabled
432 ; 9 - 15 = reserved
433 ; Note: the number of available CS pins depends on the chip used
434 ;
435 ; <q> ARBEN: Enable Bus Arbitration Pins (EBCMOD0.8)
0000 436 _ARBEN EQU 0 ; 0 = HOLD, HLDA and BREQ pins are tristate or act as GPIO
437 ; 1 = HOLD, HLDA and BREQ pins act normally
438 ;
439 ; <o> SLAVE: SLAVE mode enable (EBCMOD0.9)
440 ; <0=> Master Mode <1=> Slave Mode
0000 441 _SLAVE EQU 0 ; 0 = Bus arbiter acts in master mode
442 ; 1 = Bus arbiter acts in slave mode
443 ;
444 ; <q> EBCDIS: Disable EBC pins (EBCMOD0.10)
0000 445 _EBCDIS EQU 0 ; 0 = EBC is using the pins for external bus
446 ; 1 = EBC off (pins to be used as GPIO if implemented)
447 ;
448 ; <o> WRCFG: Configuration for pins WR/WRL and BHE/WRH (EBCMOD0.11)
449 ; <0=> WR and BHE <1=> WRL and WRH
A166 MACRO ASSEMBLER START_V2 08/30/2007 18:29:22 PAGE 8
0000 450 _WRCFG EQU 0 ; 0 = Pins act as WR and BHE
451 ; 1 = Pins act as WRL and WRH
452 ;
453 ; <q> BYTDIS: Disable BHE pin (EBCMOD0.12)
0000 454 _BYTDIS EQU 0 ; 0 = BHE enabled
455 ; 1 = BHE disabled (GPIO function if implemented)
456 ;
457 ; <q> ALEDIS: Disable ALE pin (EBCMOD0.13)
0000 458 _ALEDIS EQU 0 ; 0 = ALE pin enabled
459 ; 1 = ALE pin disabled (GPIO function if implemented)
460 ;
461 ; <q> RDYDIS: Disable READY pin (EBCMOD0.14)
0000 462 _RDYDIS EQU 0 ; 0 = READY enabled
463 ; 1 = READY disabled (GPIO function if implemented)
464 ;
465 ; <o> RDYPOL: READY pin polarity (EBCMOD0.15)
466 ; <0=> Active Low <1=> Active High
0000 467 _RDYPOL EQU 0 ; 0 = READY pin is active low
468 ; 1 = READY pin is active high
469 ;
470 ;</h>
471 ;
472 ; <h>Definitions for EBC Mode 1 register EBCMOD1
473 ; ==============================================
474 ;
475 ; <o> APDIS: Address Port Pins Disable (EBCMOD1.0 .. EBCMOD1.3) <0-15>
0000 476 _APDIS EQU 0 ; 0 = Address bus pins 15-1 of PORT1 enabled
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