📄 start_v2.lst
字号:
155 ; <q> OVRUN: Allow Pipeline Bubble Overrun (CPUCON2.4)
0001 156 _OVRUN EQU 1 ; 0 = Overrun of Pipeline Bubbles not allowed
157 ; 1 = Overrun of Pipeline Bubbles allowed
158 ;
159 ; <q> ZSC: Enable Zero Cycle Jump Cache (CPUCON2.5)
0001 160 _ZSC EQU 1 ; 0 = Zero Cycle Jump Cache disabled
161 ; 1 = Zero Cycle Jump Cache enabled
162 ;
163 ; <q> STEN: Enable Stall Instruction (CPUCON2.6)
0000 164 _STEN EQU 0 ; 0 = Stall instruction disabled
165 ; 1 = Stall instruction enabled
166 ;
167 ; <q> EIOIAEN: Early IO Injection Acknowledge guaranteed (CPUCON2.7)
0001 168 _EIOIAEN EQU 1 ; 0 = Injection ack. by destructive read not guaranteed
169 ; ; 1 = Injection ack. by destructive read guaranteed
170 ;
171 ; <q> BYPF: Enable Fetch Bypass Control (CPUCON2.8)
0001 172 _BYPF EQU 1 ; 0 = Bypass Path from Fetch to Decode disabled
173 ; 1 = Bypass Path from Fetch to Decode enabled
174 ;
175 ; <q> BYPPF: Enable Prefecth Bypass Control (CPUCON2.9)
0001 176 _BYPPF EQU 1 ; 0 = Bypass Path from Prefetch to Decode disabled
177 ; 1 = Bypass Path from Prefetch to Decode enabled
178 ;
179 ; <o> FIFOFED: FIFO Fill Configuration (CPUCON2.10 .. CPUCON2.11)
180 ; <0=> FIFO disabled <1=> 1 instruction
181 ; <2=> 2 instructions <3=> 3 instructions
0003 182 _FIFOFED EQU 3 ; 0 = FIFO disabled
183 ; 1 = FIFO filled with up to 1 instruction per cycle
184 ; 2 = FIFO filled with up to 2 instructions per cycle
185 ; 3 = FIFO filled with up to 3 instructions per cycle
186 ;
187 ;<o> FIFODEPTH: FIFO Depth Configuration (CPUCON2.12 .. CPUCON2.15) <0-8>
0008 188 _FIFODEPTH EQU 8 ; 0 = No FIFO entries (No FIFO)
189 ; 1 = 1 FIFO entry
A166 MACRO ASSEMBLER START_V2 08/30/2007 18:29:22 PAGE 4
190 ; ...
191 ; 8 = 8 FIFO entries
192 ; 9 - 15 = reserved
193 ;</e>
194 ;</h>
195 ; <h> Peripheral Configuration
196 ; ============================
197 ;
198 ; <e> Definitions for System Configuration Register SYSCON1
199 ; =========================================================
200 ;
201 ; INIT_SYSCON1: Init SYSCON1 register
202 ; --- Set INIT_SYSCON1 = 1 to initilize the SYSCON1 register
203 $SET (INIT_SYSCON1 = 0)
204 ;
205 ; <q> SLEEPCON: Sleep Mode Configuration (SYSCON1.0 .. SYSCON1.1)
206 ; <0=> IDLE mode upon IDLE instr. <1=> SLEEP mode upon IDLE instr.
0000 207 _SLEEPCON EQU 0 ; 0 = Normal IDLE mode entered upone IDLE instruction
208 ; 1 = SLEEP mode entered upon IDLE instruction
209 ; 2 - 3 = reserved
210 ;
211 ; <q> PDCFG: Port Driver Configuration (SYSCON1.2 .. SYSCON1.3)
212 ; <0=>Port drivers are always ON <1=>Port drivers are off in IDLE/Sleep mode
213 ; <2=>Port drivers are off in Powerdown mode
0000 214 _PDCFG EQU 0 ; 0 = Port drivers are always ON (default)
215 ; 1 = Port drivers are off in IDLE or Sleep mode
216 ; 2 = Port drivers are off in Powerdown mode
217 ; 3 = reserved
218 ;
219 ; <o> PFCFG: Program Flash Configuration (SYSCON1.4 .. SYSCON1.5)
220 ; <0=> Program Flash always ON <1=>Program Flash OFF in IDLE/Sleep mode
0000 221 _PFCFG EQU 0 ; 0 = Program Flash is always ON (default)
222 ; 1 = Program Flash is off in IDLE or Sleep mode
223 ; 2 - 3 = reserved
224 ;
225 ; <o> CPSYS: Clock Prescaler for System (SYSCON1.8 .. SYSCON1.10)
226 ; <0=>CPU clock = PLL frequency <1=>CPU clock = PLL frequency / 2
0000 227 _CPSYS EQU 0 ; 0 = clock signal for CPU is PLL frequency
228 ; 1 = clock signal for CPU is PLL frequency / 2
229 ; 2 - 7 = reserved
230 ; </e>
231 ;
232 ; <e> Definitions for System Configuration Register SYSCON3
233 ; =========================================================
234 ;
235 ; INIT_SYSCON3: Init SYSCON3 register
236 ; --- Set INIT_SYSCON3 = 1 to initilize the SYSCON3 register
237 $SET (INIT_SYSCON3 = 1)
238 ;
239 ; SYSCON3: Power Management (disable on-chip peripherals)
240 ;
241 ;<q> Disable Analog/Digital Converter
0000 242 ADCDIS EQU 0 ; 1 = disable Analog/Digital Converter (SYSCON3.0)
243 ;<q> Disable UART ASC0
0000 244 ASC0DIS EQU 0 ; 1 = disable UART ASC0 (SYSCON3.1)
245 ;<q> Disable Synchronus Serial Cnl0 SSC0
0000 246 SSC0DIS EQU 0 ; 1 = disable Synchronus Serial Cnl0 SSC0 (SYSCON3.2)
247 ;<q> Disable Timer Block GPT
0000 248 GPTDIS EQU 0 ; 1 = disable Timer Block GPT (SYSCON3.3)
249 ; reserved (SYSCON3.4)
250 ;<q> Disable on-chip Flash Memory Module
0000 251 FMDIS EQU 0 ; 1 = disable on-chip Flash Memory Module (SYSCON3.5)
252 ;<q> Disable CAPCOM Unit 1
0000 253 CC1DIS EQU 0 ; 1 = disable CAPCOM Unit 1 (SYSCON3.6)
254 ;<q> Disable CAPCOM Unit 2
0000 255 CC2DIS EQU 0 ; 1 = disable CAPCOM Unit 2 (SYSCON3.7)
A166 MACRO ASSEMBLER START_V2 08/30/2007 18:29:22 PAGE 5
256 ;<q> Disable CAPCOM Unit 6
0000 257 CC6DIS EQU 0 ; 1 = disable CAPCOM Unit 6 (SYSCON3.8)
258 ; reserved (SYSCON3.9)
259 ;<q> Disable UART ASC1
0000 260 ASC1DIS EQU 0 ; 1 = disable UART ASC1 (SYSCON3.10)
261 ;<q> Disable I2C Bus Module
0000 262 I2CDIS EQU 0 ; 1 = disable I2C Bus Module (SYSCON3.11)
263 ;<q> Disable SDLM (J1850) Module
0000 264 SDLMDIS EQU 0 ; 1 = disable SDLM (J1850) Module (SYSCON3.12)
265 ;<q> Disable on-chip CAN Module
0000 266 CANDIS EQU 0 ; 1 = disable on-chip CAN Module (SYSCON3.13)
267 ;<q> Disable Real Time Clock
0000 268 RTCDIS EQU 0 ; 1 = disable Real Time Clock (SYSCON3.14)
269 ;<q> Disable Synchronus Serial Cnl1 SSC1
0000 270 SSC1DIS EQU 0 ; 1 = disable Synchronus Serial Cnl1 SSC1 (SYSCON3.15)
271 ;
272 ;</e>
273 ;</h>
274 ; <e> Definitions for Reset Configuration Register RSTCON
275 ; ===================================================
276 ;
277 ; INIT_RSTCON: Init RSTCON register
278 ; --- Set INIT_RSTCON = 0 to initilize the RSTCON register
279 $SET (INIT_RSTCON = 1)
280 ;
281 ; <o> RSTLEN: Reset Length Control (RSTCON.0 .. RSTCON.2)
282 ; <0=> 2 CPU clocks <1=> 4 CPU clocks <2=> 8 CPU clocks <3=> 16 CPU clocks
283 ; <4=> 32 CPU clocks <5=> 64 CPU clocks <6=> 128 CPU clocks <7=> 256 CPU clocks
0000 284 _RSTLEN EQU 0 ; 0 = 2 t_CPU clocks (default)
285 ; 1 = 4 t_CPU clocks
286 ; 2 = 8 t_CPU clocks
287 ; 3 = 16 t_CPU clocks
288 ; 4 = 32 t_CPU clocks
289 ; 5 = 64 t_CPU clocks
290 ; 6 = 128 t_CPU clocks
291 ; 7 = 256 t_CPU clocks
292 ;
293 ; <o> RORMV: RSTOUT# Remove Control (RSTCON.4)
294 ; <0=> RSTOUT delivers RSTOUT# signal <1=> RSTOUT pin operates as GPIO
0000 295 _RORMV EQU 0 ; 0 = RSTOUT delivers RSTOUT# signal
296 ; 1 = RSTOUT pin operates as GPIO
297 ;
298 ; <o> ROCOFF: RSTOUT# Control Switch Off (RSTCON.5)
299 ; <0=>RSTOUT deactivated by user software <1=>RSTOUT deactivated after reset
0000 300 _ROCOFF EQU 0 ; 0 = RSTOUT is deactivated by user software
301 ; 1 = RSTOUT is deactivated at end of reset
302 ;
303 ; <o> ROCON: RSTOUT# Control Switch Off (RSTCON.6)
304 ; <0=> RSTOUT active on any reset <1=> RSTOUT active on hardware reset
0000 305 _ROCON EQU 0 ; 0 = RSTOUT is activated upon any reset
306 ; 1 = RSTOUT is only activated upon a hardware reset
307 ;
308 ; <q> RODIS: RSTOUT# Disable Control (RSTCON.7) <0-1>
0000 309 _RODIS EQU 0 ; 0 = RSTOUT is controlled by other mechanism
310 ; 1 = RSTOUT is deactivated
311 ;
312 ;</e>
313 ;
314 ;
315 ; <e> Definitions for PLL Control Register PLLCON
316 ; ===========================================
317 ;
318 ; INIT_PLLCON: Init PLLCON register
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -