📄 port.asm
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;****************************************************************************
; Filename PORT.asm
; Project PORT.dav
;----------------------------------------------------------------------------
; Description This file contains the assembler formatted information
; about the actual project values. It will be used by your
; programming environment.
;
; PLEASE DO NOT MODIFY THIS FILE !
;
;----------------------------------------------------------------------------
; Date 2006-07-27 9:36:40
;
;****************************************************************************
; ADC End of Conversion Interrupt Control Register
ADC_CIC_0 SET 0
ADC_CIC_GLVL SET 0
ADC_CIC_GPX SET 0
ADC_CIC_IE SET 0
ADC_CIC_ILVL SET 0
ADC_CIC_IR SET 0
; A/D Converter Control Register 1
ADC_CON1_ADCTC SET 0
ADC_CON1_ADSTC SET 0
ADC_CON1_CAL SET 0
ADC_CON1_ICST SET 0
ADC_CON1_RES SET 0
ADC_CON1_SAMPLE SET 0
; A/D Converter Control Register
ADC_CON_ADBSY SET 0
ADC_CON_ADCH SET 1
ADC_CON_ADCIN SET 0
ADC_CON_ADCRQ SET 0
ADC_CON_ADCTC SET 0
ADC_CON_ADM SET 0
ADC_CON_ADST SET 0
ADC_CON_ADSTC SET 0
ADC_CON_ADWR SET 0
; A/D Converter Control Register 0
ADC_CTR0_0 SET 0
ADC_CTR0_ADBSY SET 0
ADC_CTR0_ADCH SET 0
ADC_CTR0_ADCIN SET 0
ADC_CTR0_ADCRQ SET 0
ADC_CTR0_ADCTS SET 1
ADC_CTR0_ADM SET 0
ADC_CTR0_ADST SET 0
ADC_CTR0_ADWR SET 0
ADC_CTR0_MD SET 0
ADC_CTR0_SMPL SET 0
; A/D Converter Injection Control Register 2
ADC_CTR2IN_0 SET 0
ADC_CTR2IN_ADCTC SET 0
ADC_CTR2IN_ADSTC SET 0
ADC_CTR2IN_RES SET 0
; A/D Converter Control Register 2
ADC_CTR2_0 SET 0
ADC_CTR2_ADCTC SET 0
ADC_CTR2_ADSTC SET 0
ADC_CTR2_RES SET 0
; A/D Converter Result Register 2
ADC_DAT2_ADRES SET 0
ADC_DAT2_CHNR SET 0
; A/D Converter Result Register
ADC_DAT_ADRES SET 0
ADC_DAT_CHNR SET 0
; ADC Overrun Error Control Register
ADC_EIC_0 SET 0
ADC_EIC_GLVL SET 0
ADC_EIC_GPX SET 0
ADC_EIC_IE SET 0
ADC_EIC_ILVL SET 0
ADC_EIC_IR SET 0
; CS1 Address Range and Size Selection Register
ADDRSEL1_RGSAD1 SET 0
ADDRSEL1_RGSZ1 SET 0
; CS2 Address Range and Size Selection Register
ADDRSEL2_RGSAD2 SET 0
ADDRSEL2_RGSZ2 SET 0
; CS3 Address Range and Size Selection Register
ADDRSEL3_RGSAD3 SET 0
ADDRSEL3_RGSZ3 SET 0
; CS4 Address Range and Size Selection Register
ADDRSEL4_RGSAD4 SET 0
ADDRSEL4_RGSZ4 SET 0
; CS5 Address Range and Size Selection Register
ADDRSEL5_RGSAD5 SET 0
ADDRSEL5_RGSZ5 SET 0
; CS6 Address Range and Size Selection Register
ADDRSEL6_RGSAD6 SET 0
ADDRSEL6_RGSZ6 SET 0
; CS7 Address Range and Size Selection Register
ADDRSEL7_RGSAD7 SET 0
ADDRSEL7_RGSZ7 SET 0
; Alternate I/O Source 0 Port P1H
ALTSEL0P1H_P0 SET 0
ALTSEL0P1H_P1 SET 0
ALTSEL0P1H_P2 SET 0
ALTSEL0P1H_P3 SET 0
ALTSEL0P1H_P4 SET 0
ALTSEL0P1H_P5 SET 0
ALTSEL0P1H_P6 SET 0
ALTSEL0P1H_P7 SET 0
; P1L Alternate Select Register 0
ALTSEL0P1L_P0 SET 0
ALTSEL0P1L_P1 SET 0
ALTSEL0P1L_P2 SET 0
ALTSEL0P1L_P3 SET 0
ALTSEL0P1L_P4 SET 0
ALTSEL0P1L_P5 SET 0
ALTSEL0P1L_P6 SET 0
ALTSEL0P1L_P7 SET 0
; Alternate I/O Source Port 3 Selection
ALTSEL0P3_P1 SET 0
ALTSEL0P3_P10 SET 0
ALTSEL0P3_P11 SET 0
ALTSEL0P3_P13 SET 0
ALTSEL0P3_P3 SET 0
ALTSEL0P3_P8 SET 0
ALTSEL0P3_P9 SET 0
; Alternate I/O Source 0 Port P4
ALTSEL0P4_P6 SET 0
ALTSEL0P4_P7 SET 0
; Alternate I/O Source 0 Port P9
ALTSEL0P9_P0 SET 0
ALTSEL0P9_P1 SET 0
ALTSEL0P9_P2 SET 0
ALTSEL0P9_P3 SET 0
ALTSEL0P9_P4 SET 0
ALTSEL0P9_P5 SET 0
; Alternate I/O Source 1 Port P3
ALTSEL1P3_P1 SET 0
; Alternate I/O Source 1 Port P4
ALTSEL1P4_P7 SET 0
; Alternate I/O Source 1 Port P9
ALTSEL1P9_P0 SET 0
ALTSEL1P9_P1 SET 0
ALTSEL1P9_P2 SET 0
ALTSEL1P9_P3 SET 0
ALTSEL1P9_P4 SET 0
ALTSEL1P9_P5 SET 0
; ASC0 Autobaud Control Register
ASC0_ABCON_0 SET 0
ASC0_ABCON_0 SET 0
ASC0_ABCON_ABDETEN SET 0
ASC0_ABCON_ABEM SET 0
ASC0_ABCON_ABEN SET 0
ASC0_ABCON_ABSTEN SET 0
ASC0_ABCON_AUREN SET 0
ASC0_ABCON_FCDETEN SET 0
ASC0_ABCON_RXINV SET 0
ASC0_ABCON_TXINV SET 0
; ASC0 Autobaud Interrupt Control Register
ASC0_ABIC_0 SET 0
ASC0_ABIC_GLVL SET 0
ASC0_ABIC_GPX SET 0
ASC0_ABIC_IE SET 0
ASC0_ABIC_ILVL SET 0
ASC0_ABIC_IR SET 0
; ASC0 Autobaud Status Register
ASC0_ABSTAT_0 SET 0
ASC0_ABSTAT_DETWAIT SET 0
ASC0_ABSTAT_FCCDET SET 0
ASC0_ABSTAT_FCSDET SET 0
ASC0_ABSTAT_SCCDET SET 0
ASC0_ABSTAT_SCSDET SET 0
; Serial Channel 0 Baud Rate Generator Reload Register
ASC0_BG_0 SET 0
ASC0_BG_BR_VALUE SET 32
; Serial Channel 0 Control Register
ASC0_CON_BRS SET 0
ASC0_CON_FDE SET 0
ASC0_CON_FE SET 0
ASC0_CON_FEN SET 0
ASC0_CON_LB SET 0
ASC0_CON_M SET 1
ASC0_CON_ODD SET 0
ASC0_CON_OE SET 0
ASC0_CON_OEN SET 0
ASC0_CON_PE SET 0
ASC0_CON_PEN_RXDI SET 0
ASC0_CON_R SET 1
ASC0_CON_REN SET 0
ASC0_CON_STP SET 0
; ASC0 Error Interrupt Control Register
ASC0_EIC_0 SET 0
ASC0_EIC_GLVL SET 0
ASC0_EIC_GPX SET 0
ASC0_EIC_IE SET 0
ASC0_EIC_ILVL SET 0
ASC0_EIC_IR SET 0
; Fractional Divider Register
ASC0_FDV_0 SET 0
ASC0_FDV_FD_VALUE SET 0
; FIFO Status Register
ASC0_FSTAT_0 SET 0
ASC0_FSTAT_0 SET 0
ASC0_FSTAT_RXFFL SET 0
ASC0_FSTAT_TXFFL SET 0
; ASC0 IrDA Pulse Mode and Width Reg.
ASC0_PMW_0 SET 0
ASC0_PMW_IRPW SET 0
ASC0_PMW_PW_VALUE SET 51
; Serial Channel 0 Receiver Buffer Register (RO)
ASC0_RBUF_0 SET 0
ASC0_RBUF_RD_VALUE SET 0
; ASC0 Receive Interrupt Control Register
ASC0_RIC_0 SET 0
ASC0_RIC_GLVL SET 0
ASC0_RIC_GPX SET 0
ASC0_RIC_IE SET 0
ASC0_RIC_ILVL SET 0
ASC0_RIC_IR SET 0
; Receive FIFO Control Register
ASC0_RXFCON_0 SET 0
ASC0_RXFCON_0 SET 0
ASC0_RXFCON_RXFEN SET 0
ASC0_RXFCON_RXFFLU SET 0
ASC0_RXFCON_RXFITL SET 1
ASC0_RXFCON_RXTMEN SET 0
; ASC0 Transmit Buffer Interrupt Control Register
ASC0_TBIC_0 SET 0
ASC0_TBIC_GLVL SET 0
ASC0_TBIC_GPX SET 0
ASC0_TBIC_IE SET 0
ASC0_TBIC_ILVL SET 0
ASC0_TBIC_IR SET 0
; Serial Channel 0 Transmitter Buffer Register (WO)
ASC0_TBUF_0 SET 0
ASC0_TBUF_TD_VALUE SET 0
; ASC0 Transmit Interrupt Control Register
ASC0_TIC_0 SET 0
ASC0_TIC_GLVL SET 0
ASC0_TIC_GPX SET 0
ASC0_TIC_IE SET 0
ASC0_TIC_ILVL SET 0
ASC0_TIC_IR SET 0
; Transmit FIFO Control Register
ASC0_TXFCON_0 SET 0
ASC0_TXFCON_0 SET 0
ASC0_TXFCON_TXFEN SET 0
ASC0_TXFCON_TXFFLU SET 0
ASC0_TXFCON_TXFITL SET 1
ASC0_TXFCON_TXTMEN SET 0
; Register Bank Selection Register 0
BNKSEL0_GPRSEL0 SET 0
BNKSEL0_GPRSEL1 SET 0
BNKSEL0_GPRSEL2 SET 0
BNKSEL0_GPRSEL3 SET 0
BNKSEL0_GPRSEL4 SET 0
BNKSEL0_GPRSEL5 SET 0
BNKSEL0_GPRSEL6 SET 0
BNKSEL0_GPRSEL7 SET 0
; Register Bank Selection Register 1
BNKSEL1_GPRSEL0 SET 0
BNKSEL1_GPRSEL1 SET 0
BNKSEL1_GPRSEL2 SET 0
BNKSEL1_GPRSEL3 SET 0
BNKSEL1_GPRSEL4 SET 0
BNKSEL1_GPRSEL5 SET 0
BNKSEL1_GPRSEL6 SET 0
BNKSEL1_GPRSEL7 SET 0
; Register Bank Selection Register 2
BNKSEL2_GPRSEL0 SET 0
BNKSEL2_GPRSEL1 SET 0
BNKSEL2_GPRSEL2 SET 0
BNKSEL2_GPRSEL3 SET 0
BNKSEL2_GPRSEL4 SET 0
BNKSEL2_GPRSEL5 SET 0
BNKSEL2_GPRSEL6 SET 0
BNKSEL2_GPRSEL7 SET 0
; Register Bank Selection Register 3
BNKSEL3_GPRSEL0 SET 0
BNKSEL3_GPRSEL1 SET 0
BNKSEL3_GPRSEL2 SET 0
BNKSEL3_GPRSEL3 SET 0
BNKSEL3_GPRSEL4 SET 0
BNKSEL3_GPRSEL5 SET 0
BNKSEL3_GPRSEL6 SET 0
BNKSEL3_GPRSEL7 SET 0
; CAN Mode 0 Interrupt Control register
CAN_0IC_GLVL SET 0
CAN_0IC_GPX SET 0
CAN_0IC_IE SET 0
CAN_0IC_ILVL SET 0
CAN_0IC_IR SET 0
; CAN Mode 1 Interrupt Control register
CAN_1IC_GLVL SET 0
CAN_1IC_GPX SET 0
CAN_1IC_IE SET 0
CAN_1IC_ILVL SET 0
CAN_1IC_IR SET 0
; CAN Mode 2 Interrupt Control register
CAN_2IC_GLVL SET 0
CAN_2IC_GPX SET 0
CAN_2IC_IE SET 0
CAN_2IC_ILVL SET 0
CAN_2IC_IR SET 0
; CAN Mode 3 Interrupt Control register
CAN_3IC_GLVL SET 0
CAN_3IC_GPX SET 0
CAN_3IC_IE SET 0
CAN_3IC_ILVL SET 0
CAN_3IC_IR SET 0
; CAN Mode 4 Interrupt Control register
CAN_4IC_GLVL SET 0
CAN_4IC_GPX SET 0
CAN_4IC_IE SET 0
CAN_4IC_ILVL SET 0
CAN_4IC_IR SET 0
; CAN Mode 5 Interrupt Control register
CAN_5IC_GLVL SET 0
CAN_5IC_GPX SET 0
CAN_5IC_IE SET 0
CAN_5IC_ILVL SET 0
CAN_5IC_IR SET 0
; CAN Mode 6 Interrupt Control register
CAN_6IC_GLVL SET 0
CAN_6IC_GPX SET 0
CAN_6IC_IE SET 0
CAN_6IC_ILVL SET 0
CAN_6IC_IR SET 0
; CAN Mode 7 Interrupt Control register
CAN_7IC_GLVL SET 0
CAN_7IC_GPX SET 0
CAN_7IC_IE SET 0
CAN_7IC_ILVL SET 0
CAN_7IC_IR SET 0
; Node A Bit Timing Register High
CAN_ABTRH_LBM SET 0
; Node A Bit Timing Register Low
CAN_ABTRL_BRP SET 1
CAN_ABTRL_DIV8X SET 0
CAN_ABTRL_SJW SET 1
CAN_ABTRL_TSEG1 SET 5
CAN_ABTRL_TSEG2 SET 2
; Node A Control Register
CAN_ACR_CALM SET 0
CAN_ACR_CCE SET 0
CAN_ACR_EIE SET 0
CAN_ACR_INIT SET 1
CAN_ACR_LECIE SET 0
CAN_ACR_SIE SET 0
; Node A Error Counter Register High
CAN_AECNTH_EWRNLVL SET 96
CAN_AECNTH_LEINC SET 0
CAN_AECNTH_LETD SET 0
; Node A Error Counter Register Low
CAN_AECNTL_REC SET 0
CAN_AECNTL_TEC SET 0
; Node A Frame Counter Register High
CAN_AFCRH_CFCIE SET 0
CAN_AFCRH_CFCMD SET 0
CAN_AFCRH_CFCOV SET 0
; Node A Frame Counter Register Low
CAN_AFCRL_CFC SET 0
; Node A Global Interrupt Node Pointer Register
CAN_AGINP_CFCINP SET 0
CAN_AGINP_EINP SET 0
CAN_AGINP_LECINP SET 0
CAN_AGINP_TRINP SET 0
; Node A INTID Mask Register 4 Low
CAN_AIMR4_IMC32 SET 0
CAN_AIMR4_IMC33 SET 0
CAN_AIMR4_IMC34 SET 0
; Node A INTID Mask Register 0 High
CAN_AIMRH0_IMC16 SET 0
CAN_AIMRH0_IMC17 SET 0
CAN_AIMRH0_IMC18 SET 0
CAN_AIMRH0_IMC19 SET 0
CAN_AIMRH0_IMC20 SET 0
CAN_AIMRH0_IMC21 SET 0
CAN_AIMRH0_IMC22 SET 0
CAN_AIMRH0_IMC23 SET 0
CAN_AIMRH0_IMC24 SET 0
CAN_AIMRH0_IMC25 SET 0
CAN_AIMRH0_IMC26 SET 0
CAN_AIMRH0_IMC27 SET 0
CAN_AIMRH0_IMC28 SET 0
CAN_AIMRH0_IMC29 SET 0
CAN_AIMRH0_IMC30 SET 0
CAN_AIMRH0_IMC31 SET 0
; Node A INTID Mask Register 0 Low
CAN_AIMRL0_IMC0 SET 0
CAN_AIMRL0_IMC1 SET 0
CAN_AIMRL0_IMC10 SET 0
CAN_AIMRL0_IMC11 SET 0
CAN_AIMRL0_IMC12 SET 0
CAN_AIMRL0_IMC13 SET 0
CAN_AIMRL0_IMC14 SET 0
CAN_AIMRL0_IMC15 SET 0
CAN_AIMRL0_IMC2 SET 0
CAN_AIMRL0_IMC3 SET 0
CAN_AIMRL0_IMC4 SET 0
CAN_AIMRL0_IMC5 SET 0
CAN_AIMRL0_IMC6 SET 0
CAN_AIMRL0_IMC7 SET 0
CAN_AIMRL0_IMC8 SET 0
CAN_AIMRL0_IMC9 SET 0
; Node A Interrupt Pending Register
CAN_AIR_0 SET 0
CAN_AIR_INTID SET 0
; Node A Status Register
CAN_ASR_BOFF SET 0
CAN_ASR_EWRN SET 0
CAN_ASR_LEC SET 0
CAN_ASR_RXOK SET 0
CAN_ASR_TXOK SET 0
; Node B Bit Timing Register High
CAN_BBTRH_LBM SET 0
; Node B Bit Timing Register Low
CAN_BBTRL_BRP SET 1
CAN_BBTRL_DIV8X SET 0
CAN_BBTRL_SJW SET 1
CAN_BBTRL_TSEG1 SET 4
CAN_BBTRL_TSEG2 SET 3
; Node B Control Register
CAN_BCR_CALM SET 0
CAN_BCR_CCE SET 0
CAN_BCR_EIE SET 0
CAN_BCR_INIT SET 1
CAN_BCR_LECIE SET 0
CAN_BCR_SIE SET 0
; Node B Error Counter Register High
CAN_BECNTH_EWRNLVL SET 96
CAN_BECNTH_LEINC SET 0
CAN_BECNTH_LETD SET 0
; Node B Error Counter Register Low
CAN_BECNTL_REC SET 96
CAN_BECNTL_TEC SET 0
; Node B Frame Counter Register High
CAN_BFCRH_CFCIE SET 0
CAN_BFCRH_CFCMD SET 0
CAN_BFCRH_CFCOV SET 0
; Node B Frame Counter Register Low
CAN_BFCRL_CFC SET 0
; Node B Global Interrupt Node Pointer Register
CAN_BGINP_CFCINP SET 0
CAN_BGINP_EINP SET 0
CAN_BGINP_LECINP SET 0
CAN_BGINP_TRINP SET 0
; Node B INTID Mask Register 4 Low
CAN_BIMR4_IMC32 SET 0
CAN_BIMR4_IMC33 SET 0
CAN_BIMR4_IMC34 SET 0
; Node B INTID Mask Register 0 High
CAN_BIMRH0_IMC16 SET 0
CAN_BIMRH0_IMC17 SET 0
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