start_v2.a66

英飞凌C166之XC164CS的IO读写操作程序

$MODV2                                  ; Define C166v2 core mode
;
;------------------------------------------------------------------------------
;  This file is part of the C166 Compiler package
;  Copyright KEIL ELEKTRONIK GmbH 1993 - 2004
;  Version 5.05
;  Note:  PHAx default set to 0 as bypass for TwinCAN device problem.
;  *** <<< Use Configuration Wizard in Context Menu >>> ***
;
;------------------------------------------------------------------------------
;  START_V2.A66:  This code is executed after processor reset and provides the
;                 startup sequence for the C166v2/Super10 architecture CPU's.
;                 (i.e. XC161, XC164, XC167, ect.)
;
;  You may add this file to a uVision2 project - in this case it will be 
;  automatically assembled and linked.
;
;  For manual translation of this file use A166 with the following invocation:
;
;     A166 START_V2.A66 SET (model)
;
;     model determines the memory model and can be one of the following:
;         TINY, SMALL, COMPACT, HCOMPACT, MEDIUM, LARGE, HLARGE, XLARGE
;
;  Example:  A166 START_V2.A66 SET (SMALL)
;
;  For manual linkage of the modified START_V2.OBJ file to your application
;  use the following L166 invocation:
;
;     L166 your object file list, START_V2.OBJ controls
;
;------------------------------------------------------------------------------
; Setup model-dependend Assembler controls
$CASE
$IF NOT TINY
$SEGMENTED
$ENDIF
; Settings for ADDRSEL calculation (do not change!)
KB          EQU    0x400     ; define KB constant for CS _SIZE calculation
MB          EQU    0x400*KB  ; define MB as 1024KB
;------------------------------------------------------------------------------
;
; <h>Definitions for System and User Stack
; ========================================
;
; <o>STKSZ: Maximum System Stack Size selection <0x0-0x1000:0x2>
; <i> Defines the system stack space that is used by CALL/RET and PUSH/POP
; <i> instructions.  The system stack space must be adjusted according the actual
; <i> requirements of the application.
SSTSZ   EQU     0x200 
; <o> USTSZ: User Stack Size Definition <0x0-0x4000:0x2>
; <i> Defines the user stack space available for automatics.  This stack space is
; <i> accessed by R0.  The user stack space must be adjusted according the actual
; <i> requirements of the application.
USTSZ   EQU     0x200    ; set User Stack Size to 200H Bytes.
;
; <o> UST1SZ: User Stack Size for local register bank 1 <0x0-0x4000:0x2>
; <i> Defines the user stack space available for the interrupt functions that are
; <i> assigned to the local register bank 1.  Since the compiler cannot copy the R0
; <i> value to local register banks, the user stack must be assign separately.
; <i> If you have no interrupt functions assigned to local register bank 1, you may
; <i> set UST1SZ to 0.
UST1SZ   EQU    0x20     ; set User Stack Size to 20H Bytes.
;
; <o> UST2SZ: User Stack Size for local register bank 2 <0x0-0x4000:0x2>
; <i> Defines the user stack space available for the interrupt functions that are
; <i> assigned to the local register bank 1.  Since the compiler cannot copy the R0
; <i> value to local register banks, the user stack must be assign separately.
;  If you have no interrupt functions assigned to local register bank 2, you may
;  set UST2SZ to 0.
UST2SZ   EQU    0x20     ; set User Stack Size to 20H Bytes.
;
; </h>
; <h>Definitions for Startup Code
; ===============================
;
; <q> CLR_MEMORY: Enable/Disable Memory Zero Initialization of RAM area
; --- <i> Set CLR_MEMORY = 0 to disable memory zero initilization
$SET (CLR_MEMORY = 1)
;
; <q> INIT_VARS: Enable/Disable Variable Initialization
; --- <i> Set INIT_VARS = 0 to disable variable initilization
$SET (INIT_VARS = 1)
;
; <q> DPPUSE:  Allow re-assign of DPP registers 
; --- <i> Set DPPUSE = 0 to reduce the code size of the startup code, if you
;     <i> are not using the L166 DPPUSE directive.
$SET (DPPUSE = 1)
;
; <q> DPP3USE: Use DPP3 register during variable initilization
; --- <i> Set DPP3USE = 0 to disable the usage of DPP3 during initilization of
;     <i> variables.  This option might be required if you write
;     <i> program parts that are reloaded during application 
;     <i> execution and increase code size of the startup code.
$SET (DPP3USE = 1)
;
;</h>
; <h> CPU Configuration
; =====================
;
; <h> Definitions for CPU Configuration Register CPUCON1
; ======================================================
;
; <q> ZCJ: Enable Zero Cycle Jump Function (CPUCON1.0):
_ZCJ EQU 1 ; 0 = Disable Zero Cycle Jump Function /Dave/     
                        ; 1 = Enable Zero Cycle Jump Function
;
; <q> BP: Enable Branch Prediction Unit (CPUCON1.1):
_BP EQU 1 ; 0 = Disable Branch Prediction Unit /Dave/     
                        ; 1 = Enable Branch Prediction Unit
;
; <q> INTSCXT: Enable Interruptability of Switch Context Instruction (CPUCON1.2):
_INTSCXT EQU 1 ; 0 = Disable Interruption of SCXT instruction /Dave/     
                        ; 1 = Enable Interruption of SCXT instruction
;
; SGTDIS: Disable Segmentation Control (CPUCON1.3):
$IF TINY
_SGTDIS EQU 0 ; disable segmented mode for TINY model /Dave/     
$ELSE
_SGTDIS  EQU    0       ; enable segmented mode (Reset Value)
$ENDIF
;
; <o> WDTCTL: Watchdog Timer Control (CPUCON1.4):
; <0=> DISWDT executable until end of EINIT  <1=> DISWDT/ENWDT always executable
_WDTCTL EQU 0 ; 0 = DISWDT executable until end of EINIT /Dave/     
                        ; 1 = DISWDT/ENWDT always executable
;
; <o> VECSC: Vector Table Scaling Factor (CPUCON1.5 .. CPUCON1.6)
; <0=> 2 words  <1=> 4 words  <2=> 8 words  <3=> 16 words
_VECSC EQU 0 ; 0 = Space between two vectors is 2 words /Dave/     
                        ; 1 = Space between two vectors is 4 words
                        ; 2 = Space between two vectors is 8 words
                        ; 3 = Space between two vectors is 16 words
;
; </h>
; <e> Definitions for CPU Configuration Register CPUCON2
; ======================================================
;
;  INIT_CPUCON2: Init CPUCON2 register
; --- <i>Set INIT_CPUCON2 to initilize the CPUCON2 register
$SET (INIT_CPUCON2 = 0) ; default: do not initilize CPUCON2  
;
; <q> SL: Enable Short Loop Mode (CPUCON2.0)
_SL EQU 1 ; 0 = Short Loop mode disabled /Dave/     
                        ; 1 = Short Loop mode enabled
;
; <q> DIAD: Disable Atomic Injection Deny (CPUCON2.1)
_DIAD  EQU   1          ; 0 = Injection-requests are denied during Atomic 
                        ; 1 = Injection-requests are not denied during Atomic 
;
; <q> RETST: Enable Return Stack (CPUCON2.3)
_RETST EQU 1 ; 0 = Return Stack disabled /Dave/     
                        ; 1 = Return Stack enabled
;
; <q> OVRUN: Allow Pipeline Bubble Overrun (CPUCON2.4)
_OVRUN EQU 1 ; 0 = Overrun of Pipeline Bubbles not allowed /Dave/     
                        ; 1 = Overrun of Pipeline Bubbles allowed
;
; <q> ZSC: Enable Zero Cycle Jump Cache (CPUCON2.5)
_ZSC      EQU   1       ; 0 = Zero Cycle Jump Cache disabled
                        ; 1 = Zero Cycle Jump Cache enabled
;
; <q> STEN: Enable Stall Instruction (CPUCON2.6)
_STEN EQU 0 ; 0 = Stall instruction disabled /Dave/     
                        ; 1 = Stall instruction enabled
;
; <q> EIOIAEN: Early IO Injection Acknowledge guaranteed (CPUCON2.7)
_EIOIAEN  EQU   1       ; 0 = Injection ack. by destructive read not guaranteed
;                       ; 1 = Injection ack. by destructive read guaranteed
; 
; <q> BYPF: Enable Fetch Bypass Control (CPUCON2.8)
_BYPF EQU 1 ; 0 = Bypass Path from Fetch to Decode disabled /Dave/     
                        ; 1 = Bypass Path from Fetch to Decode enabled
;
; <q> BYPPF: Enable Prefecth Bypass Control (CPUCON2.9)
_BYPPF EQU 1 ; 0 = Bypass Path from Prefetch to Decode disabled /Dave/     
                        ; 1 = Bypass Path from Prefetch to Decode enabled
;
; <o> FIFOFED: FIFO Fill Configuration (CPUCON2.10 .. CPUCON2.11)
; <0=> FIFO disabled    <1=> 1 instruction
; <2=> 2 instructions   <3=> 3 instructions
_FIFOFED EQU 3 ; 0 = FIFO disabled /Dave/     
                        ; 1 = FIFO filled with up to 1 instruction per cycle
                        ; 2 = FIFO filled with up to 2 instructions per cycle
                        ; 3 = FIFO filled with up to 3 instructions per cycle
;
;<o> FIFODEPTH: FIFO Depth Configuration (CPUCON2.12 .. CPUCON2.15) <0-8>
_FIFODEPTH EQU 8 ; 0 = No FIFO entries (No FIFO) /Dave/     
                        ; 1 = 1 FIFO entry
                        ; ...
                        ; 8 = 8 FIFO entries
                        ; 9 - 15 = reserved
;</e>

; <e> Definitions for Internal Memory Block Control Register IMBCTR
; =================================================================
;
;  INIT_IMBCTR: Init IMBCTR register
; --- <i>Set INIT_IMBCTR to initilize the IMBCTR register
$SET (INIT_IMBCTR = 0)  ; default: do not initilize IMBCTR  
;
; <o> WSFLASH: Wait States for the Flash Memory (IMBCTR.0 .. IMBCTR.1)
; <0=> No waitstates (Flash Read in one clock)
; <1=> One waitstate (Flash Read in two clocks)
; <2=> Two waitstates (Flash Read in three clocks)
; <3=> Three waitstates (Flash Read in four clocks)
_WSFLASH  EQU   1       ; 0 = No waitstates
                        ; 1 = One waitstate
                        ; 2 = Two waitstates
                        ; 3 = Three waitstates
;
; <q> WSRAM: Wait State for Program RAM Access (IMBCTR.2)
; <i> when enabled, Program SRAM has same timing behaviour as Flash memory
_WSRAM    EQU   0       ; 0 = Program SRAM accessed with max. speed
                        ; 1 = Program SRAM access like Flash Memory
;
;</e>

;</h>
; <h> Peripheral Configuration
; ============================
;
; <e> Definitions for System Configuration Register SYSCON1
; =========================================================
;
; INIT_SYSCON1: Init SYSCON1 register
; --- Set INIT_SYSCON1 = 1 to initilize the SYSCON1 register
$SET (INIT_SYSCON1 = 0) ; /Dave/     
;
; <q> SLEEPCON: Sleep Mode Configuration (SYSCON1.0 .. SYSCON1.1)
; <0=> IDLE mode upon IDLE instr. <1=> SLEEP mode upon IDLE instr.
_SLEEPCON EQU 0 ; 0 = Normal IDLE mode entered upone IDLE instruction /Dave/     
                        ; 1 = SLEEP mode entered upon IDLE instruction
                        ; 2 - 3 = reserved
;
; <q> PDCFG: Port Driver Configuration (SYSCON1.2 .. SYSCON1.3)
; <0=>Port drivers are always ON <1=>Port drivers are off in IDLE/Sleep mode
; <2=>Port drivers are off in Powerdown mode
_PDCFG EQU 0 ; 0 = Port drivers are always ON (default) /Dave/     
                        ; 1 = Port drivers are off in IDLE or Sleep mode
                        ; 2 = Port drivers are off in Powerdown mode
                        ; 3 = reserved
;
; <o> PFCFG: Program Flash Configuration (SYSCON1.4 .. SYSCON1.5) 
; <0=> Program Flash always ON <1=>Program Flash OFF in IDLE/Sleep mode
_PFCFG EQU 0 ; 0 = Program Flash is always ON (default) /Dave/     
                        ; 1 = Program Flash is off in IDLE or Sleep mode
                        ; 2 - 3 = reserved
;
; <o> CPSYS: Clock Prescaler for System (SYSCON1.8 .. SYSCON1.10)
; <0=>CPU clock = PLL frequency  <1=>CPU clock = PLL frequency / 2
_CPSYS EQU 0 ; 0 = clock signal for CPU is PLL frequency /Dave/     
                        ; 1 = clock signal for CPU is PLL frequency / 2
                        ; 2 - 7 = reserved
; </e>
;
; <e> Definitions for System Configuration Register SYSCON3
; =========================================================
;
; INIT_SYSCON3: Init SYSCON3 register
; --- Set INIT_SYSCON3 = 1 to initilize the SYSCON3 register
$SET (INIT_SYSCON3 = 1) ; /Dave/     
;
; SYSCON3:  Power Management (disable on-chip peripherals)
;
;<q> Disable Analog/Digital Converter
ADCDIS  EQU     0       ; 1 = disable Analog/Digital Converter    (SYSCON3.0)
;<q> Disable UART ASC0
ASC0DIS EQU 1 ; 1 = disable UART ASC0                   (SYSCON3.1) /Dave/     
;<q> Disable Synchronus Serial Cnl0 SSC0
SSC0DIS EQU 1 ; 1 = disable Synchronus Serial Cnl0 SSC0 (SYSCON3.2) /Dave/     
;<q> Disable Timer Block GPT 
GPTDIS EQU 1 ; 1 = disable Timer Block GPT             (SYSCON3.3) /Dave/     
                        ; reserved                                (SYSCON3.4)
;<q> Disable on-chip Flash Memory Module
FMDIS EQU 0 ; 1 = disable on-chip Flash Memory Module (SYSCON3.5) /Dave/     
;<q> Disable CAPCOM Unit 1
CC1DIS EQU 1 ; 1 = disable CAPCOM Unit 1               (SYSCON3.6) /Dave/     
;<q> Disable CAPCOM Unit 2
CC2DIS EQU 1 ; 1 = disable CAPCOM Unit 2               (SYSCON3.7) /Dave/     
;<q> Disable CAPCOM Unit 6
CC6DIS EQU 1 ; 1 = disable CAPCOM Unit 6               (SYSCON3.8) /Dave/     
                        ; reserved                                (SYSCON3.9)
;<q> Disable UART ASC1
ASC1DIS EQU 0 ; 1 = disable UART ASC1                   (SYSCON3.10) /Dave/     
;<q> Disable I2C Bus Module
I2CDIS EQU 0 ; 1 = disable I2C Bus Module              (SYSCON3.11) /Dave/     
;<q> Disable SDLM (J1850) Module
SDLMDIS EQU 0 ; 1 = disable SDLM (J1850) Module         (SYSCON3.12) /Dave/     
;<q> Disable on-chip CAN Module
CANDIS EQU 1 ; 1 = disable on-chip CAN Module          (SYSCON3.13) /Dave/     
;<q> Disable Real Time Clock
RTCDIS  EQU     0       ; 1 = disable Real Time Clock             (SYSCON3.14)
;<q> Disable Synchronus Serial Cnl1 SSC1
SSC1DIS EQU 1 ; 1 = disable Synchronus Serial Cnl1 SSC1 (SYSCON3.15) /Dave/     
;
;</e>
;</h>
; <e> Definitions for Reset Configuration Register RSTCON
; =======================================================
;
; INIT_RSTCON: Init RSTCON register
; --- Set INIT_RSTCON = 0 to initilize the RSTCON register
$SET (INIT_RSTCON = 0) ; /Dave/     
;