dm9000.c

dm9000aep linux2.6驱动

{
	int tx_status = ior(db, DM9000_NSR);	/* Got TX status */

	if (tx_status & (NSR_TX2END | NSR_TX1END)) {
		/* One packet sent complete */
		db->tx_pkt_cnt--;
		db->stats.tx_packets++;

		/* Queue packet check & send */
		if (db->tx_pkt_cnt > 0) {
			iow(db, DM9000_TXPLL, db->queue_pkt_len & 0xff);
			iow(db, DM9000_TXPLH, (db->queue_pkt_len >> 8) & 0xff);
			iow(db, DM9000_TCR, TCR_TXREQ);
			dev->trans_start = jiffies;
		}
		netif_wake_queue(dev);
	}
}

static irqreturn_t
dm9000_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	struct net_device *dev = dev_id;
	board_info_t *db;
	int int_status;
	u8 reg_save;

	PRINTK3("entering %s\n",__FUNCTION__);

	if (!dev) {
		PRINTK1("dm9000_interrupt() without DEVICE arg\n");
		return IRQ_HANDLED;
	}

	/* A real interrupt coming */
	db = (board_info_t *) dev->priv;
	spin_lock(&db->lock);

	/* Save previous register address */
	reg_save = readb(db->io_addr);

	/* Disable all interrupts */
	iow(db, DM9000_IMR, IMR_PAR);

	/* Got DM9000 interrupt status */
	int_status = ior(db, DM9000_ISR);	/* Got ISR */
	iow(db, DM9000_ISR, int_status);	/* Clear ISR status */

	/* Received the coming packet */
	if (int_status & ISR_PRS)
		dm9000_rx(dev);

	/* Trnasmit Interrupt check */
	if (int_status & ISR_PTS)
		dm9000_tx_done(dev, db);

	/* Re-enable interrupt mask */
	iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);

	/* Restore previous register address */
	writeb(reg_save, db->io_addr);

	spin_unlock(&db->lock);

	return IRQ_HANDLED;
}

/*
 *  Get statistics from driver.
 */
static struct net_device_stats *
dm9000_get_stats(struct net_device *dev)
{
	board_info_t *db = (board_info_t *) dev->priv;
	return &db->stats;
}


/*
 *  A periodic timer routine
 *  Dynamic media sense, allocated Rx buffer...
 */
static void
dm9000_timer(unsigned long data)
{
	struct net_device *dev = (struct net_device *) data;
	board_info_t *db = (board_info_t *) dev->priv;

	PRINTK3("dm9000_timer()\n");

	mii_check_media(&db->mii, netif_msg_link(db), 0);

	/* Set timer again */
	db->timer.expires = DM9000_TIMER_WUT;
	add_timer(&db->timer);
}

struct dm9000_rxhdr {
	u16	RxStatus;
	u16	RxLen;
} __attribute__((__packed__));

/*
 *  Received a packet and pass to upper layer
 */
static void
dm9000_rx(struct net_device *dev)
{
	board_info_t *db = (board_info_t *) dev->priv;
	struct dm9000_rxhdr rxhdr;
	struct sk_buff *skb;
	u8 rxbyte, *rdptr;
	int GoodPacket;
	int RxLen;

	/* Check packet ready or not */
	do {
		ior(db, DM9000_MRCMDX);	/* Dummy read */

		/* Get most updated data */
		rxbyte = readb(db->io_data);

		/* Status check: this byte must be 0 or 1 */
		if (rxbyte > DM9000_PKT_RDY) {
			printk("status check failed: %d\n", rxbyte);
			iow(db, DM9000_RCR, 0x00);	/* Stop Device */
			iow(db, DM9000_ISR, IMR_PAR);	/* Stop INT request */
			return;
		}

		if (rxbyte != DM9000_PKT_RDY)
			return;

		/* A packet ready now  & Get status/length */
		GoodPacket = TRUE;
		writeb(DM9000_MRCMD, db->io_addr);

		(db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr));

		RxLen = rxhdr.RxLen;

		/* Packet Status check */
		if (RxLen < 0x40) {
			GoodPacket = FALSE;
			PRINTK1("Bad Packet received (runt)\n");
		}

		if (RxLen > DM9000_PKT_MAX) {
			PRINTK1("RST: RX Len:%x\n", RxLen);
		}

		if (rxhdr.RxStatus & 0xbf00) {
			GoodPacket = FALSE;
			if (rxhdr.RxStatus & 0x100) {
				PRINTK1("fifo error\n");
				db->stats.rx_fifo_errors++;
			}
			if (rxhdr.RxStatus & 0x200) {
				PRINTK1("crc error\n");
				db->stats.rx_crc_errors++;
			}
			if (rxhdr.RxStatus & 0x8000) {
				PRINTK1("length error\n");
				db->stats.rx_length_errors++;
			}
		}

		/* Move data from DM9000 */
		if (GoodPacket
		    && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) {
			skb->dev = dev;
			skb_reserve(skb, 2);
			rdptr = (u8 *) skb_put(skb, RxLen - 4);

			/* Read received packet from RX SRAM */

			(db->inblk)(db->io_data, rdptr, RxLen);
			db->stats.rx_bytes += RxLen;

			/* Pass to upper layer */
			skb->protocol = eth_type_trans(skb, dev);
			netif_rx(skb);
			db->stats.rx_packets++;

		} else {
			/* need to dump the packet's data */

			(db->dumpblk)(db->io_data, RxLen);
		}
	} while (rxbyte == DM9000_PKT_RDY);
}
#if 0
/*
 *  Read a word data from SROM
 */
static u16
read_srom_word(board_info_t * db, int offset)
{
	iow(db, DM9000_EPAR, offset);
	iow(db, DM9000_EPCR, EPCR_ERPRR);
	mdelay(8);		/* according to the datasheet 200us should be enough,
				   but it doesn't work */
	iow(db, DM9000_EPCR, 0x0);
	return (ior(db, DM9000_EPDRL) + (ior(db, DM9000_EPDRH) << 8));
}
#endif
#ifdef DM9000_PROGRAM_EEPROM
/*
 * Write a word data to SROM
 */
static void
write_srom_word(board_info_t * db, int offset, u16 val)
{
	iow(db, DM9000_EPAR, offset);
	iow(db, DM9000_EPDRH, ((val >> 8) & 0xff));
	iow(db, DM9000_EPDRL, (val & 0xff));
	iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);
	mdelay(8);		/* same shit */
	iow(db, DM9000_EPCR, 0);
}

/*
 * Only for development:
 * Here we write static data to the eeprom in case
 * we don't have valid content on a new board
 */
static void
program_eeprom(board_info_t * db)
{
	u16 eeprom[] = { 0x0c00, 0x007f, 0x1300,	/* MAC Address */
		0x0000,		/* Autoload: accept nothing */
		0x0a46, 0x9000,	/* Vendor / Product ID */
		0x0000,		/* pin control */
		0x0000,
	};			/* Wake-up mode control */
	int i;
	for (i = 0; i < 8; i++)
		write_srom_word(db, i, eeprom[i]);
}
#endif


/*
 *  Calculate the CRC valude of the Rx packet
 *  flag = 1 : return the reverse CRC (for the received packet CRC)
 *         0 : return the normal CRC (for Hash Table index)
 */

static unsigned long
cal_CRC(unsigned char *Data, unsigned int Len, u8 flag)
{

       u32 crc = ether_crc_le(Len, Data);

       if (flag)
               return ~crc;

       return crc;
}

/*
 *  Set DM9000 multicast address
 */
static void
dm9000_hash_table(struct net_device *dev)
{
	board_info_t *db = (board_info_t *) dev->priv;
	struct dev_mc_list *mcptr = dev->mc_list;
	int mc_cnt = dev->mc_count;
	u32 hash_val;
	u16 i, oft, hash_table[4];
	unsigned long flags;

	PRINTK2("dm9000_hash_table()\n");

	spin_lock_irqsave(&db->lock,flags);

	for (i = 0, oft = 0x10; i < 6; i++, oft++)
		iow(db, oft, dev->dev_addr[i]);

	/* Clear Hash Table */
	for (i = 0; i < 4; i++)
		hash_table[i] = 0x0;

	/* broadcast address */
	hash_table[3] = 0x8000;

	/* the multicast address in Hash Table : 64 bits */
	for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
		hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f;
		hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
	}

	/* Write the hash table to MAC MD table */
	for (i = 0, oft = 0x16; i < 4; i++) {
		iow(db, oft++, hash_table[i] & 0xff);
		iow(db, oft++, (hash_table[i] >> 8) & 0xff);
	}

	spin_unlock_irqrestore(&db->lock,flags);
}


/*
 *   Read a word from phyxcer
 */
static int
dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
{
	board_info_t *db = (board_info_t *) dev->priv;
	unsigned long flags;
	unsigned int reg_save;
	int ret;

	spin_lock_irqsave(&db->lock,flags);

	/* Save previous register address */
	reg_save = readb(db->io_addr);

	/* Fill the phyxcer register into REG_0C */
	iow(db, DM9000_EPAR, DM9000_PHY | reg);

	iow(db, DM9000_EPCR, 0xc);	/* Issue phyxcer read command */
	udelay(100);		/* Wait read complete */
	iow(db, DM9000_EPCR, 0x0);	/* Clear phyxcer read command */

	/* The read data keeps on REG_0D & REG_0E */
	ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);

	/* restore the previous address */
	writeb(reg_save, db->io_addr);

	spin_unlock_irqrestore(&db->lock,flags);

	return ret;
}

/*
 *   Write a word to phyxcer
 */
static void
dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value)
{
	board_info_t *db = (board_info_t *) dev->priv;
	unsigned long flags;
	unsigned long reg_save;

	spin_lock_irqsave(&db->lock,flags);

	/* Save previous register address */
	reg_save = readb(db->io_addr);

	/* Fill the phyxcer register into REG_0C */
	iow(db, DM9000_EPAR, DM9000_PHY | reg);

	/* Fill the written data into REG_0D & REG_0E */
	iow(db, DM9000_EPDRL, (value & 0xff));
	iow(db, DM9000_EPDRH, ((value >> 8) & 0xff));

	iow(db, DM9000_EPCR, 0xa);	/* Issue phyxcer write command */
	udelay(500);		/* Wait write complete */
	iow(db, DM9000_EPCR, 0x0);	/* Clear phyxcer write command */

	/* restore the previous address */
	writeb(reg_save, db->io_addr);

	spin_unlock_irqrestore(&db->lock,flags);
}

static int
dm9000_drv_suspend(struct device *dev, pm_message_t state, u32 level)
{
	struct net_device *ndev = dev_get_drvdata(dev);

	if (ndev && level == SUSPEND_DISABLE) {
		if (netif_running(ndev)) {
			netif_device_detach(ndev);
			dm9000_shutdown(ndev);
		}
	}
	return 0;
}

static int
dm9000_drv_resume(struct device *dev, u32 level)
{
	struct net_device *ndev = dev_get_drvdata(dev);
	board_info_t *db = (board_info_t *) ndev->priv;

	if (ndev && level == RESUME_ENABLE) {

		if (netif_running(ndev)) {
			dm9000_reset(db);
			dm9000_init_dm9000(ndev);

			netif_device_attach(ndev);
		}
	}
	return 0;
}

static int
dm9000_drv_remove(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct net_device *ndev = dev_get_drvdata(dev);

	dev_set_drvdata(dev, NULL);

	unregister_netdev(ndev);
	dm9000_release_board(pdev, (board_info_t *) ndev->priv);
	kfree(ndev);		/* free device structure */

	PRINTK1("clean_module() exit\n");

	return 0;
}

static struct device_driver dm9000_driver = {
	.name    = "dm9000",
	.bus     = &platform_bus_type,
	.probe   = dm9000_probe,
	.remove  = dm9000_drv_remove,
	.suspend = dm9000_drv_suspend,
	.resume  = dm9000_drv_resume,
};

static int __init
dm9000_init(void)
{
	printk(KERN_INFO "%s Ethernet Driver\n", CARDNAME);
	
       dm9000_cpu_init();
	   
	return driver_register(&dm9000_driver);	/* search board and register */
}

static void __exit
dm9000_cleanup(void)
{
	driver_unregister(&dm9000_driver);
}

module_init(dm9000_init);
module_exit(dm9000_cleanup);

MODULE_AUTHOR("Sascha Hauer, Ben Dooks");
MODULE_DESCRIPTION("Davicom DM9000 network driver");
MODULE_LICENSE("GPL");