syslib.c

在Tornado环境下实现的8139网卡芯片的驱动程序

    INT_NUM_IOAPIC_IRQ5,		/* IO APIC IRQ  5 Vector No */
    INT_NUM_IOAPIC_IRQ6,		/* IO APIC IRQ  6 Vector No */
    INT_NUM_IOAPIC_IRQ7,		/* IO APIC IRQ  7 Vector No */
    INT_NUM_IOAPIC_IRQ8,		/* IO APIC IRQ  8 Vector No */
    INT_NUM_IOAPIC_IRQ9,		/* IO APIC IRQ  9 Vector No */
    INT_NUM_IOAPIC_IRQA,		/* IO APIC IRQ 10 Vector No */
    INT_NUM_IOAPIC_IRQB,		/* IO APIC IRQ 11 Vector No */
    INT_NUM_IOAPIC_IRQC,		/* IO APIC IRQ 12 Vector No */
    INT_NUM_IOAPIC_IRQD,		/* IO APIC IRQ 13 Vector No */
    INT_NUM_IOAPIC_IRQE,		/* IO APIC IRQ 14 Vector No */
    INT_NUM_IOAPIC_IRQF,		/* IO APIC IRQ 15 Vector No */
    INT_NUM_IOAPIC_PIRQA,		/* IO APIC PIRQ A Vector No */
    INT_NUM_IOAPIC_PIRQB,		/* IO APIC PIRQ B Vector No */
    INT_NUM_IOAPIC_PIRQC,		/* IO APIC PIRQ C Vector No */
    INT_NUM_IOAPIC_PIRQD,		/* IO APIC PIRQ D Vector No */
    INT_NUM_IOAPIC_PIRQE,		/* IO APIC PIRQ E Vector No */
    INT_NUM_IOAPIC_PIRQF,		/* IO APIC PIRQ F Vector No */
    INT_NUM_IOAPIC_PIRQG,		/* IO APIC PIRQ G Vector No */
    INT_NUM_IOAPIC_PIRQH,		/* IO APIC PIRQ H Vector No */
    INT_NUM_LOAPIC_TIMER,		/* Local APIC Timer Vector No */
    INT_NUM_LOAPIC_ERROR,		/* Local APIC Error Vector No */
    INT_NUM_LOAPIC_LINT0,		/* Local APIC LINT0 Vector No */
    INT_NUM_LOAPIC_LINT1,		/* Local APIC LINT1 Vector No */
    INT_NUM_LOAPIC_PMC,			/* Local APIC PMC Vector No */
    INT_NUM_LOAPIC_THERMAL,		/* Local APIC Thermal Vector No */
    INT_NUM_LOAPIC_SPURIOUS,		/* Local APIC Spurious Vector No */
    INT_NUM_LOAPIC_SM,			/* Local APIC SM Vector No */
    INT_NUM_LOAPIC_SM + 1,		/* Local APIC SM Vector No */
    INT_NUM_LOAPIC_SM + 2,		/* Local APIC SM Vector No */
    INT_NUM_LOAPIC_SM + 3,		/* Local APIC SM Vector No */
    INT_NUM_LOAPIC_IPI,			/* Local APIC IPI Vector No */
    INT_NUM_LOAPIC_IPI + 1,		/* Local APIC IPI Vector No */
    INT_NUM_LOAPIC_IPI + 2,		/* Local APIC IPI Vector No */
    INT_NUM_LOAPIC_IPI + 3,		/* Local APIC IPI Vector No */
    INT_NUM_LOAPIC_IPI + 4,		/* Local APIC IPI Vector No */
    INT_NUM_LOAPIC_IPI + 5,		/* Local APIC IPI Vector No */
    INT_NUM_LOAPIC_IPI + 6,		/* Local APIC IPI Vector No */
    INT_NUM_LOAPIC_IPI + 7		/* Local APIC IPI Vector No */
    };

#else

UINT8	sysInumTbl[]	=  		/* IRQ vs IntNum table */
    {
    INT_NUM_IRQ0,			/* IRQ  0 Vector No */
    INT_NUM_IRQ0 + 1,			/* IRQ  1 Vector No */
    INT_NUM_IRQ0 + 2,			/* IRQ  2 Vector No */
    INT_NUM_IRQ0 + 3,			/* IRQ  3 Vector No */
    INT_NUM_IRQ0 + 4,			/* IRQ  4 Vector No */
    INT_NUM_IRQ0 + 5,			/* IRQ  5 Vector No */
    INT_NUM_IRQ0 + 6,			/* IRQ  6 Vector No */
    INT_NUM_IRQ0 + 7,			/* IRQ  7 Vector No */
    INT_NUM_IRQ0 + 8,			/* IRQ  8 Vector No */
    INT_NUM_IRQ0 + 9,			/* IRQ  9 Vector No */
    INT_NUM_IRQ0 + 10,			/* IRQ 10 Vector No */
    INT_NUM_IRQ0 + 11,			/* IRQ 11 Vector No */
    INT_NUM_IRQ0 + 12,			/* IRQ 12 Vector No */
    INT_NUM_IRQ0 + 13,			/* IRQ 13 Vector No */
    INT_NUM_IRQ0 + 14,			/* IRQ 14 Vector No */
    INT_NUM_IRQ0 + 15,			/* IRQ 15 Vector No */
    };

#endif	/* defined(VIRTUAL_WIRE_MODE) */

UINT32 sysInumTblNumEnt	= NELEMENTS (sysInumTbl);


/* locals */

#ifdef	INCLUDE_ROMCARD

LOCAL short *sysRomBase[] = 
    {
    (short *)0xce000, (short *)0xce800, (short *)0xcf000, (short *)0xcf800
    };

LOCAL char sysRomSignature[ROM_SIGNATURE_SIZE] = 
    {
    0x55,0xaa,0x01,0x90,0x90,0x90,0x90,0x90,
    0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90
    };

#endif	/* INCLUDE_ROMCARD */

#if	(CPU == PENTIUM2) || (CPU == PENTIUM3) || (CPU == PENTIUM4)
    /*
     * The cache control flags and MTRRs operate hierarchically for restricting
     * caching.  That is, if the CD flag is set, caching is prevented globally.
     * If the CD flag is clear, either the PCD flags and/or the MTRRs can be
     * used to restrict caching.  If there is an overlap of page-level caching
     * control and MTRR caching control, the mechanism that prevents caching
     * has precedence.  For example, if an MTRR makes a region of system memory
     * uncachable, a PCD flag cannot be used to enable caching for a page in 
     * that region.  The converse is also true; that is, if the PCD flag is 
     * set, an MTRR cannot be used to make a region of system memory cacheable.
     * If there is an overlap in the assignment of the write-back and write-
     * through caching policies to a page and a region of memory, the write-
     * through policy takes precedence.  The write-combining policy takes
     * precedence over either write-through or write-back.
     */ 
LOCAL MTRR sysMtrr =
    { 					/* MTRR table */
    {0,0},				/* MTRR_CAP register */
    {0,0},				/* MTRR_DEFTYPE register */
    					/* Fixed Range MTRRs */
    {{{MTRR_WB, MTRR_WB, MTRR_WB, MTRR_WB, MTRR_WB, MTRR_WB, MTRR_WB, MTRR_WB}},
     {{MTRR_WB, MTRR_WB, MTRR_WB, MTRR_WB, MTRR_WB, MTRR_WB, MTRR_WB, MTRR_WB}},
     {{MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_WC, MTRR_WC, MTRR_WC, MTRR_WC}},
     {{MTRR_WP, MTRR_WP, MTRR_WP, MTRR_WP, MTRR_WP, MTRR_WP, MTRR_WP, MTRR_WP}},
     {{MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC}},
     {{MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC}},
     {{MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC}},
     {{MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC}},
     {{MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC}},
     {{MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC}},
     {{MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC, MTRR_UC}}},
    {{0LL, 0LL},			/* Variable Range MTRRs */
     {0LL, 0LL},
     {0LL, 0LL},
     {0LL, 0LL},
     {0LL, 0LL},
     {0LL, 0LL},
     {0LL, 0LL},
     {0LL, 0LL}}
    };
#endif  /* (CPU == PENTIUM[2/3/4]) */


/* forward declarations */

LOCAL void sysStrayInt   (void);
char * sysPhysMemTop	 (void);
STATUS sysMmuMapAdd	 (void * address, UINT len, UINT initialStateMask,
                    	  UINT initialState);
LOCAL void sysIntInitPIC (void);
LOCAL void sysIntEoiGet  (VOIDFUNCPTR * vector, 
			  VOIDFUNCPTR * routineBoi, int * parameterBoi,
			  VOIDFUNCPTR * routineEoi, int * parameterEoi);


/* includes (source file) */

#if (NV_RAM_SIZE != NONE)
#   include "sysNvRam.c"
#else	/* default to nullNvRam */
#   include "mem/nullNvRam.c"
#endif	/* (NV_RAM_SIZE != NONE) */

#include "sysSerial.c"

#if	defined (TGT_CPU) && defined (SYMMETRIC_IO_MODE)
#   include "sysAmp.c"
#else
#   include "vme/nullVme.c"
#endif	/* defined (TGT_CPU) && defined (SYMMETRIC_IO_MODE) */

#if	defined(VIRTUAL_WIRE_MODE)
#   include "intrCtl/loApicIntr.c"
#   include "intrCtl/i8259Intr.c"
#   ifdef INCLUDE_APIC_TIMER
#      include "timer/loApicTimer.c"	/* includes timestamp driver */
#   else
#      include "timer/i8253Timer.c"	/* includes timestamp driver */
#   endif /* INCLUDE_APIC_TIMER */
#   ifdef INCLUDE_SHOW_ROUTINES
#      include "intrCtl/loApicIntrShow.c"
#   endif /* INCLUDE_SHOW_ROUTINES */
#elif	defined(SYMMETRIC_IO_MODE)
#   include "intrCtl/loApicIntr.c"
#   include "intrCtl/i8259Intr.c"
#   include "intrCtl/ioApicIntr.c"
#   ifdef INCLUDE_APIC_TIMER
#      include "timer/loApicTimer.c"	/* includes timestamp driver */
#   else
#      include "timer/i8253Timer.c"	/* includes timestamp driver */
#   endif /* INCLUDE_APIC_TIMER */
#   ifdef INCLUDE_SHOW_ROUTINES
#      include "intrCtl/loApicIntrShow.c"
#      include "intrCtl/ioApicIntrShow.c"
#   endif /* INCLUDE_SHOW_ROUTINES */
#else
#   include "intrCtl/i8259Intr.c"
#   include "timer/i8253Timer.c"	/* includes timestamp driver */
#endif	/* defined(VIRTUAL_WIRE_MODE) */

#ifdef	INCLUDE_PCI                     /* BSP PCI bus & config support */
#   include "pciCfgStub.c"              /* customize pciConfigLib for BSP */
#   include "pci/pciConfigLib.c"
#   include "pciCfgIntStub.c"           /* customize pciIntLib for BSP */
#   include "pci/pciIntLib.c"
#   if (defined(INCLUDE_PCI_CFGSHOW) && !defined(PRJ_BUILD))
#      include "pci/pciConfigShow.c"
#   endif /* (defined(INCLUDE_PCI_CFGSHOW) && !defined(PRJ_BUILD)) */
#if (PCI_CFG_TYPE == PCI_CFG_AUTO)
#   include "pci/pciAutoConfigLib.c"
#   include "sysBusPci.c"
#endif /* (PCI_CFG_TYPE == PCI_CFG_AUTO) */
#endif	/* INCLUDE_PCI */

#ifdef	INCLUDE_PCMCIA
#   include "pcmcia/pccardLib.c"
#   include "pcmcia/pccardShow.c"
#endif	/* INCLUDE_PCMCIA */

#ifdef  INCLUDE_NETWORK
#   include "sysNet.c"                  /* network driver support */
#endif  /* INCLUDE_NETWORK */

#ifdef INCLUDE_RTL_81X9_END
#include "sysRtl81x9End.c"
#endif /* INCLUDE_RTL_81X9_END */

/* include dm9102End driver support routines */

#ifdef INCLUDE_DM_9102_END
#include "sysDm9102End.c"
#endif /* INCLUDE_DM_9102_END */

#if defined(INCLUDE_SCSI) || defined(INCLUDE_SCSI2)
#    include "sysScsi.c"                /* scsi support */
#endif /* INCLUDE_SCSI || INCLUDE_SCSI2 */

/* include BSP specific WindML configuration */

#if defined(INCLUDE_WINDML)
#    include "sysWindML.c"
#endif /* INCLUDE_WINDML */

/*******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string "PC 386, 486, PENTIUM or PENTIUM[234]".
*/

char *sysModel (void)

    {
#if	(CPU == I80386)
    return ("PC 386");
#elif	(CPU == I80486)
    return ("PC 486");
#elif	(CPU == PENTIUM)
    return ("PC PENTIUM");
#elif	(CPU == PENTIUM2)
    return ("PC PENTIUM2");
#elif	(CPU == PENTIUM3)
    return ("PC PENTIUM3");
#elif	(CPU == PENTIUM4)
    return ("PC PENTIUM4");
#endif	/* (CPU == I80386) */
    }

/*******************************************************************************
*
* sysBspRev - return the BSP version and revision number
*
* This routine returns a pointer to a BSP version and revision number, for
* example, 1.1/0. BSP_REV is concatenated to BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }

#ifdef INCLUDE_SYS_HW_INIT_0

/*******************************************************************************
*
* sysHwInit0 - BSP-specific hardware initialization
*
* This routine is called from usrInit() to perform BSP-specific initialization
* that must be done before cacheLibInit() is called and/or the BSS is cleared.
*
* The BSP-specific sysCpuProbe() routine is called for the purpose of
* identifying IA-32 target CPU variants, and the features or functions
* supported by the target CPU.  This information must be obtained relatively
* early during system hardware initialization, as some support libraries
* (mmuLib, cacheLib, &c.) will use the processor feature information to
* enable or disable architecture-specific and/or BSP-specific functionality.
*
* RETURNS: N/A
*
* NOMANUAL
*/

void sysHwInit0 (void)
    {
    (void) sysCpuProbe ();
    }

#endif  /* INCLUDE_SYS_HW_INIT_0 */

/*******************************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes various features of the i386/i486 board.
* It is called from usrInit() in usrConfig.c.
*
* NOTE: This routine should not be called directly by the user application.
*
* RETURNS: N/A
*/

void sysHwInit (void)
    {
    PHYS_MEM_DESC *pMmu;
    int ix = 0;

#if	(CPU == PENTIUM) || (CPU == PENTIUM2) || (CPU == PENTIUM3) || \
	(CPU == PENTIUM4)

    /* initialize the MSRs (Model Specific Registers) */
    
    pentiumMsrInit ();

#   if	(CPU != PENTIUM)

    /* enable the MTRR (Memory Type Range Registers) */

    if ((sysCpuId.featuresEdx & CPUID_MTRR) == CPUID_MTRR)
	{
        pentiumMtrrDisable ();		/* disable MTRR */
#   ifdef INCLUDE_MTRR_GET
        (void) pentiumMtrrGet (&sysMtrr); /* get MTRR initialized by BIOS */
#   else
        (void) pentiumMtrrSet (&sysMtrr); /* set your own MTRR */
#   endif /* INCLUDE_MTRR_GET */
        pentiumMtrrEnable ();		/* enable MTRR */
	}

#   endif /* (CPU != PENTIUM) */

#   ifdef INCLUDE_PMC

    /* enable PMC (Performance Monitoring Counters) */

    pentiumPmcStop ();			/* stop PMC0 and PMC1 */
    pentiumPmcReset ();			/* reset PMC0 and PMC1 */

#   endif /* INCLUDE_PMC */

    /* enable the MCA (Machine Check Architecture) */

    pentiumMcaEnable (TRUE);

#   ifdef INCLUDE_SHOW_ROUTINES

    /* 
     * if excMcaInfoShow is not NULL, it is called in the default
     * exception handler when Machine Check Exception happened
     */

    {
    IMPORT FUNCPTR excMcaInfoShow;
    excMcaInfoShow = (FUNCPTR) pentiumMcaShow;
    }

    vxShowInit ();

#   endif /* INCLUDE_SHOW_ROUTINES */

#endif	/* (CPU == PENTIUM) || (CPU == PENTIUM[234]) */

    /* initialize the number of active mappings (sysPhysMemDescNumEnt) */

    pMmu = &sysPhysMemDesc[0];

    for (ix = 0; ix < NELEMENTS (sysPhysMemDesc); ix++)