tb_mul.v

这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.

module tb_mul;
parameter length=32;
reg[length-1:0] a_i,b_i;
reg             clk_i;
wire[2*length-1:0]i;
wire[2*length-1:0]mul_o;
//wire[1:0]         div_quotien_o,div_remainder_o;
mul32x32 mul_inst(a_i,b_i,mul_o);

//div div_inst(a_i,b_i,clk_i,div_quotien_o,div_remainder_o);

assign i=a_i*b_i;

initial
 begin
		clk_i = 1'b0;
		forever #50 clk_i= ~clk_i;

end

initial 
	begin
	  a_i=32'h0000_0000;
   	forever #10 a_i=a_i+1;
end 

initial 
	begin
    b_i=32'h0000_0000;
		forever #60 b_i=b_i+1;	
end 



 initial
	 begin
      $fsdbDumpfile("test_mul.fsdb");
      $fsdbDumpvars;
   		#10000 $finish;
   end

 endmodule