tb_bootmul.v

来自「这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对」· Verilog 代码 · 共 44 行

module tb_bootmul;
reg[31:0]a_i,b_i;
reg      clk_i,sign_i;
wire[63:0]mul_o;   
wire[63:0]mul_tree;
wire[63:0]sign_b;

boot_mul instant(a_i,b_i,clk_i,sign_i,mul_o,sign_b,mul_tree);

initial 
begin
      a_i=32'hffff_ffff;
      forever #10 a_i=a_i-1;
end

initial 
begin
      b_i=1;
      forever #50 b_i=b_i+1;
end

initial 
begin
      clk_i=0;
      forever #20 clk_i=clk_i+1;
end

initial 
begin
      sign_i=0;
      forever #200 sign_i=sign_i+1;
end


 initial
	 begin
      $fsdbDumpfile("test_boot.fsdb");
      $fsdbDumpvars;
   		#10000 $finish;
   end

endmodule