std8980.vhd

TDS510仿真器 的硬件电路和软件VHDL代码和大家共享.有兴趣可以自己动手做

        VARIABLE RDY_zd         : std_ulogic;
        VARIABLE TDOint         : std_ulogic;
        VARIABLE TDO_zd         : std_ulogic;
        VARIABLE TCKint         : std_ulogic;
        VARIABLE TCK_zd         : std_ulogic;
        VARIABLE TMSint         : std_ulogic;
        VARIABLE TMS_zd         : std_ulogic;
        VARIABLE TRSTint        : std_ulogic;
        VARIABLE TRST_zd        : std_ulogic;

        -- No Weak Values Variables
        VARIABLE RW_nwv      : UX01 := 'U';
        VARIABLE RST_nwv     : UX01 := 'U';
        VARIABLE TOE_nwv     : UX01 := 'U';
        VARIABLE TDI_nwv     : UX01 := 'U';

        -- Output Glitch Detection Variables
        VARIABLE D0_GlitchData     : VitalGlitchDataType;
        VARIABLE D1_GlitchData     : VitalGlitchDataType;
        VARIABLE D2_GlitchData     : VitalGlitchDataType;
        VARIABLE D3_GlitchData     : VitalGlitchDataType;
        VARIABLE D4_GlitchData     : VitalGlitchDataType;
        VARIABLE D5_GlitchData     : VitalGlitchDataType;
        VARIABLE D6_GlitchData     : VitalGlitchDataType;
        VARIABLE D7_GlitchData     : VitalGlitchDataType;
        VARIABLE RDY_GlitchData   : VitalGlitchDataType;
        VARIABLE TDO_GlitchData   : VitalGlitchDataType;
        VARIABLE TCK_GlitchData   : VitalGlitchDataType;
        VARIABLE TMS_GlitchData   : VitalGlitchDataType;
        VARIABLE TRST_GlitchData  : VitalGlitchDataType;

        -- Other Variables
        VARIABLE tck_cnt     : natural;
        VARIABLE prev_CDIV   : natural;
        VARIABLE tck_div     : natural;
        VARIABLE addr        : natural;

    BEGIN
        RW_nwv    := To_UX01 (s => RW);
        RST_nwv   := To_UX01 (s => RSTNeg);
        TOE_nwv   := To_UX01 (s => TOENeg);
        TDI_nwv   := To_UX01 (s => TDI);
        CDIV := to_nat(configB(7 downto 5));
        OPCOD := to_nat(command(3 downto 0));

        --------------------------------------------------------------------
        -- Timing Check Section
        --------------------------------------------------------------------
        IF (TimingChecksOn) THEN

        VitalSetupHoldCheck (
            TestSignal      => RW,
            TestSignalName  => "RW",
            RefSignal       => STRBNeg,
            RefSignalName   => "STRBNeg",
            SetupHigh       => tsetup_RW_STRBNeg,
            SetupLow        => tsetup_RW_STRBNeg,
            CheckEnabled    => TRUE,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & partID,
            TimingData      => TD_RW_STRBNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_RW_STRBNeg_su
        );

        VitalSetupHoldCheck (
            TestSignal      => RW,
            TestSignalName  => "RW",
            RefSignal       => STRBNeg,
            RefSignalName   => "STRBNeg",
            HoldHigh        => thold_RW_STRBNeg,
            HoldLow         => thold_RW_STRBNeg,
            CheckEnabled    => TRUE,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & partID,
            TimingData      => TD_RW_STRBNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_RW_STRBNeg_hd
        );

        VitalSetupHoldCheck (
            TestSignal      => Address,
            TestSignalName  => "A",
            RefSignal       => STRBNeg,
            RefSignalName   => "STRBNeg",
            SetupHigh       => tsetup_A0_STRBNeg,
            SetupLow        => tsetup_A0_STRBNeg,
            CheckEnabled    => TRUE,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & partID,
            TimingData      => TD_A_STRBNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_A_STRBNeg_su
        );

        VitalSetupHoldCheck (
            TestSignal      => Address,
            TestSignalName  => "A",
            RefSignal       => STRBNeg,
            RefSignalName   => "STRBNeg",
            HoldHigh        => thold_A0_STRBNeg,
            HoldLow         => thold_A0_STRBNeg,
            CheckEnabled    => TRUE,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & partID,
            TimingData      => TD_A_STRBNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_A_STRBNeg_hd
        );

        VitalSetupHoldCheck (
            TestSignal      => DataIn,
            TestSignalName  => "D",
            RefSignal       => STRBNeg,
            RefSignalName   => "STRBNeg",
            SetupHigh       => tsetup_D0_STRBNeg,
            SetupLow        => tsetup_D0_STRBNeg,
            HoldHigh        => thold_D0_STRBNeg,
            HoldLow         => thold_D0_STRBNeg,
            CheckEnabled    => (RW_nwv = '0'),
            RefTransition   => '/',
            HeaderMsg       => InstancePath & partID,
            TimingData      => TD_D_STRBNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_D_STRBNeg
        );

        VitalSetupHoldCheck (
            TestSignal      => TDI,
            TestSignalName  => "TDI",
            RefSignal       => CLKIN,
            RefSignalName   => "CLKIN",
            SetupHigh       => tsetup_TDI_CLKIN,
            SetupLow        => tsetup_TDI_CLKIN,
            HoldHigh        => thold_TDI_CLKIN,
            HoldLow         => thold_TDI_CLKIN,
            CheckEnabled    => TRUE,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & partID,
            TimingData      => TD_TDI_CLKIN,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_TDI_CLKIN
        );

        VitalPeriodPulseCheck (
            TestSignal      => RSTNeg,
            TestSignalName  => "RSTNeg",
            PulseWidthLow   => tpw_RSTNeg_negedge,
            CheckEnabled    => TRUE,
            HeaderMsg       => InstancePath & partID,
            PeriodData      => PD_RSTNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Pviol_RSTNeg
        );

        VitalPeriodPulseCheck (
            TestSignal      => STRBNeg,
            TestSignalName  => "STRBNeg",
            PulseWidthLow   => tpw_STRBNeg_negedge,
            CheckEnabled    => TRUE,
            HeaderMsg       => InstancePath & partID,
            PeriodData      => PD_STRBNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Pviol_STRBNeg
        );


        VitalPeriodPulseCheck (
            TestSignal      => CLKIN,
            TestSignalName  => "CLKIN",
            Period          => tperiod_CLKIN_z1,
            PulseWidthHigh  => tpw_CLKIN_z1,
            PulseWidthLow   => tpw_CLKIN_z1,
            CheckEnabled    => (CDIV = 0),
            HeaderMsg       => InstancePath & partID,
            PeriodData      => PD_CLKIN,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Pviol_CLKIN0
        );

        VitalPeriodPulseCheck (
            TestSignal      => CLKIN,
            TestSignalName  => "CLKIN",
            Period          => tperiod_CLKIN_1z,
            PulseWidthHigh  => tpw_CLKIN_1z,
            PulseWidthLow   => tpw_CLKIN_1z,
            CheckEnabled    => (CDIV = 1),
            HeaderMsg       => InstancePath & partID,
            PeriodData      => PD_CLKIN,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Pviol_CLKIN1
        );

        VitalPeriodPulseCheck (
            TestSignal      => CLKIN,
            TestSignalName  => "CLKIN",
            Period          => tperiod_CLKIN_z0,
            PulseWidthHigh  => tpw_CLKIN_z0,
            PulseWidthLow   => tpw_CLKIN_z0,
            CheckEnabled    => (CDIV > 1),
            HeaderMsg       => InstancePath & partID,
            PeriodData      => PD_CLKIN,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Pviol_CLKIN2
        );


            Violation := Tviol_A_STRBNeg_su OR Tviol_A_STRBNeg_hd OR
                         Tviol_D_STRBNeg OR Tviol_RW_STRBNeg_su OR
                         Tviol_RW_STRBNeg_hd OR Pviol_RSTNeg OR Pviol_STRBNeg
                         OR Tviol_TDI_CLKIN OR Pviol_CLKIN0 OR Pviol_CLKIN1
                         OR Pviol_CLKIN2;

        END IF; -- Timing Check Section

        --------------------------------------------------------------------
        -- Functional Section
        --------------------------------------------------------------------
        -- Power Up & Reset
        IF NOW = 0 ns OR RST_nwv = '0' OR SWRST = '1' THEN
            configA := "00000000";
            configB := "10000000";
            status  := "00000000";
            command := "00000000";
            tdobuf  := "00000000";
            tdibuf  := "00000000";
            counter := "00000000";
            control := "00000000";
            Counter_reg := (others => "00000000");
            TDI_fifo  := (others => "00000000");
            TDO_fifo  := (others => "00000000");
            TDO_empty := true;
            tdiincnt  := 0;
            tdioutcnt := 0;
            tdibitcnt := 0;
            tdoincnt  := 0;
            tdooutcnt := 0;
            tdobitcnt := 0;
            Count     := 0;
            countercnt := 0;
            RDYint  := '1';
            TDOint  := '1';
            TMSint  := '1';
            TRSTint := '1';
            TCKint  := '0';
            CDIV := 4;
            tck_cnt := 0;
            TAP_state := Test_Logic_Reset;
            clkrun := true;
            OP_done := true;
        END IF;

        -- Host Interface
        IF falling_edge(STRBNeg) THEN
            addr := to_nat(Address);
            IF RW_nwv = '1' THEN        -- read
                IF addr = 5 THEN
                    IF TDIS = '0' THEN
                        RDYint := '0';
                    ELSE
                        tdibuf := TDI_fifo(tdioutcnt);
                        DOut_zd := tdibuf;
                        IF tdioutcnt = 3 THEN
                            tdioutcnt := 0;
                        ELSE
                            tdioutcnt := tdioutcnt + 1;
                        END IF;
                        IF tdioutcnt = tdiincnt THEN
                            TDIS := '0';
                        END IF;
                    END IF;
                ELSIF addr = 6 THEN
                    counter := Counter_reg(countercnt);
                    DOut_zd := counter;
                    IF countercnt = 3 THEN
                        countercnt := 0;
                    ELSE
                        countercnt := countercnt + 1;
                    END IF;
                ELSE
                    DOut_zd := Reg(addr);
                END IF;
            ELSIF RW_nwv = '0' THEN     -- write
                IF addr = 2 OR addr = 5 THEN
                    ASSERT false
                        REPORT "Illegal write attemped"
                        SEVERITY ERROR;
                ELSIF addr = 4 THEN
                    IF TDOS = '1' THEN
                        RDYint := '0';
                    END IF;
                ELSIF addr = 3 THEN
                    IF OPCOD /= 0 THEN
                        RDYint := '0';
                    END IF;
                ELSIF addr < 2 AND OPCOD /= 0 THEN
                    RDYint := '0';
                END IF;
            ELSE                        -- error
                ASSERT false
                    REPORT "RW in unusable state during STRBNeg"
                    SEVERITY ERROR;
            END IF;
        ELSIF rising_edge(STRBNeg) THEN
            IF RW_nwv = '1' THEN        -- read
                DOut_zd := (others => 'Z');
                IF addr = 7 AND MODE = "010" THEN
                    TCKint := '1';
                END IF;
            ELSIF RW_nwv = '0'AND RDYint = '1' THEN     -- write
                IF addr = 4 THEN
                    tdobuf := DataIn;
                    TDO_fifo(tdoincnt) := tdobuf;
                    clkrun := true;
                    TDO_empty := false;
                    IF tdoincnt = 3 THEN
                        tdoincnt := 0;
                    ELSE
                        tdoincnt := tdoincnt + 1;
                    END IF;
                    IF tdoincnt = tdooutcnt THEN
                        TDOS := '1';
                    END IF;
                ELSIF addr = 6 THEN
                    counter := DataIn;
                    Counter_reg(countercnt) := counter;
                    IF countercnt = 3 THEN
                        countercnt := 0;
                        CTRS := '1';
                        Count := to_nat(Counter_reg(3) & Counter_reg(2) &
                                        Counter_reg(1) & Counter_reg(0));
                    ELSE
                        countercnt := countercnt + 1;
                    END IF;
                ELSIF addr = 3 THEN
                    command := DataIn;
                    OPCOD := to_nat(command(3 downto 0));
                    IF OPCOD /= 0 THEN
                        TDI_fifo  := (others => "00000000");
                        TDO_fifo  := (others => "00000000");