std8980.vhd

TDS510仿真器 的硬件电路和软件VHDL代码和大家共享.有兴趣可以自己动手做

--------------------------------------------------------------------------------
--  File Name: std8980.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2001 Free Model Foundry; http://vhdl.org/fmf/
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    01 Jan 08   Initial release
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    PROCESSOR
--  Technology: 74xx
--  Part:       STD8980
-- 
--  Description: JTAG Tap Master w/ 8-Bit Host I/F
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY std8980 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_D0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_RW                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_TDI                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLKIN               : VitalDelayType01 := VitalZeroDelay01;
        tipd_STRBNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_RSTNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_TOENeg              : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CLKIN_TDO            : VitalDelayType01 := UnitDelay01;
        tpd_CLKIN_TCK            : VitalDelayType01 := UnitDelay01;
        tpd_STRBNeg_D0           : VitalDelayType01Z := UnitDelay01Z;
        tpd_STRBNeg_RDY          : VitalDelayType01 := UnitDelay01;
        tpd_STRBNeg_TDO          : VitalDelayType01Z := UnitDelay01Z;
        tpd_STRBNeg_TMS          : VitalDelayType01Z := UnitDelay01Z; --dc
        tpd_RSTNeg_D0            : VitalDelayType01 := UnitDelay01;
        tpd_RSTNeg_RDY           : VitalDelayType01 := UnitDelay01;
        tpd_RSTNeg_TDO           : VitalDelayType01 := UnitDelay01;
        tpd_RSTNeg_TCK           : VitalDelayType01 := UnitDelay01;
        tpd_TOENeg_TDO           : VitalDelayType01Z := UnitDelay01Z;
        -- tsetup values: setup times
        tsetup_D0_STRBNeg        : VitalDelayType := UnitDelay;
        tsetup_A0_STRBNeg        : VitalDelayType := UnitDelay;
        tsetup_RW_STRBNeg        : VitalDelayType := UnitDelay;
        tsetup_TDI_CLKIN         : VitalDelayType := UnitDelay;
        -- thold values: hold times
        thold_D0_STRBNeg         : VitalDelayType := UnitDelay;
        thold_A0_STRBNeg         : VitalDelayType := UnitDelay;
        thold_RW_STRBNeg         : VitalDelayType := UnitDelay;
        thold_TDI_CLKIN          : VitalDelayType := UnitDelay;
        -- tpw values: pulse widths
        tpw_CLKIN_z1          : VitalDelayType := UnitDelay;
        tpw_CLKIN_1z          : VitalDelayType := UnitDelay;
        tpw_CLKIN_z0          : VitalDelayType := UnitDelay;
        tpw_RSTNeg_negedge    : VitalDelayType := UnitDelay;
        tpw_STRBNeg_negedge   : VitalDelayType := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_CLKIN_z1      : VitalDelayType := UnitDelay;
        tperiod_CLKIN_1z      : VitalDelayType := UnitDelay;
        tperiod_CLKIN_z0      : VitalDelayType := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        D0              : INOUT std_ulogic := 'U';
        D1              : INOUT std_ulogic := 'U';
        D2              : INOUT std_ulogic := 'U';
        D3              : INOUT std_ulogic := 'U';
        D4              : INOUT std_ulogic := 'U';
        D5              : INOUT std_ulogic := 'U';
        D6              : INOUT std_ulogic := 'U';
        D7              : INOUT std_ulogic := 'U';
        A0              : IN    std_ulogic := 'U';
        A1              : IN    std_ulogic := 'U';
        A2              : IN    std_ulogic := 'U';
        RW              : IN    std_ulogic := 'U';
        TDI             : IN    std_ulogic := 'H';
        CLKIN           : IN    std_ulogic := 'U';
        RDY             : OUT   std_ulogic := 'U';
        TDO             : OUT   std_ulogic := 'U';
        TMS             : OUT   std_ulogic := 'U';
        TCK             : OUT   std_ulogic := 'U';
        STRBNeg         : IN    std_ulogic := 'H';
        RSTNeg          : IN    std_ulogic := 'H';
        TOENeg          : IN    std_ulogic := 'H';
        TRSTNeg         : OUT   std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of std8980 : ENTITY IS TRUE;
END std8980;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of std8980 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID            : STRING := "STD8980";

    SIGNAL D0_ipd              : std_ulogic := 'U';
    SIGNAL D1_ipd              : std_ulogic := 'U';
    SIGNAL D2_ipd              : std_ulogic := 'U';
    SIGNAL D3_ipd              : std_ulogic := 'U';
    SIGNAL D4_ipd              : std_ulogic := 'U';
    SIGNAL D5_ipd              : std_ulogic := 'U';
    SIGNAL D6_ipd              : std_ulogic := 'U';
    SIGNAL D7_ipd              : std_ulogic := 'U';
    SIGNAL A0_ipd              : std_ulogic := 'U';
    SIGNAL A1_ipd              : std_ulogic := 'U';
    SIGNAL A2_ipd              : std_ulogic := 'U';
    SIGNAL RW_ipd              : std_ulogic := 'U';
    SIGNAL TDI_ipd             : std_ulogic := 'U';
    SIGNAL CLKIN_ipd           : std_ulogic := 'U';
    SIGNAL STRBNeg_ipd         : std_ulogic := 'U';
    SIGNAL RSTNeg_ipd          : std_ulogic := 'U';
    SIGNAL TOENeg_ipd          : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (D0_ipd, D0, tipd_D0);
        w_2 : VitalWireDelay (D1_ipd, D1, tipd_D1);
        w_3 : VitalWireDelay (D2_ipd, D2, tipd_D2);
        w_4 : VitalWireDelay (D3_ipd, D3, tipd_D3);
        w_5 : VitalWireDelay (D4_ipd, D4, tipd_D4);
        w_6 : VitalWireDelay (D5_ipd, D5, tipd_D5);
        w_7 : VitalWireDelay (D6_ipd, D6, tipd_D6);
        w_8 : VitalWireDelay (D7_ipd, D7, tipd_D7);
        w_9 : VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_10 : VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_11 : VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_12 : VitalWireDelay (RW_ipd, RW, tipd_RW);
        w_13 : VitalWireDelay (TDI_ipd, TDI, tipd_TDI);
        w_14 : VitalWireDelay (CLKIN_ipd, CLKIN, tipd_CLKIN);
        w_19 : VitalWireDelay (STRBNeg_ipd, STRBNeg, tipd_STRBNeg);
        w_20 : VitalWireDelay (RSTNeg_ipd, RSTNeg, tipd_RSTNeg);
        w_21 : VitalWireDelay (TOENeg_ipd, TOENeg, tipd_TOENeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent procedure calls
    ----------------------------------------------------------------------------

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            Address         : IN    std_logic_vector(2 downto 0);
            DataIn          : IN    std_logic_vector(7 downto 0);
            DataOut         : OUT   std_logic_vector(7 downto 0);
            RDY             : OUT   std_ulogic := 'U';
            TDO             : OUT   std_ulogic := 'U';
            TMS             : OUT   std_ulogic := 'U';
            TCK             : OUT   std_ulogic := 'U';
            TRSTNeg         : OUT   std_ulogic := 'U';
            RW              : IN    std_ulogic := 'U';
            TDI             : IN    std_ulogic := 'H';
            CLKIN           : IN    std_ulogic := 'U';
            RSTNeg          : IN    std_ulogic := 'H';
            TOENeg          : IN    std_ulogic := 'H';
            STRBNeg         : IN    std_ulogic := 'H'
        );
        PORT MAP (
            DataOut(0) =>  D0,
            DataOut(1) =>  D1,
            DataOut(2) =>  D2,
            DataOut(3) =>  D3,
            DataOut(4) =>  D4,
            DataOut(5) =>  D5,
            DataOut(6) =>  D6,
            DataOut(7) =>  D7,
            DataIn(0) =>  D0_ipd,
            DataIn(1) =>  D1_ipd,
            DataIn(2) =>  D2_ipd,
            DataIn(3) =>  D3_ipd,
            DataIn(4) =>  D4_ipd,
            DataIn(5) =>  D5_ipd,
            DataIn(6) =>  D6_ipd,
            DataIn(7) =>  D7_ipd,
            Address(0) => A0_ipd,
            Address(1) => A1_ipd,
            Address(2) => A2_ipd,
            RW => RW_ipd,
            TDI => TDI_ipd,
            CLKIN => CLKIN_ipd,
            RSTNeg => RSTNeg_ipd,
            TOENeg => TOENeg_ipd,
            TDO => TDO,
            TMS => TMS,
            TRSTNeg => TRSTNeg,
            RDY => RDY,
            TCK => TCK,
            STRBNeg    => STRBNeg_ipd
        );

    SIGNAL TCKsig : std_ulogic;

    BEGIN

    TCK <= TCKsig;

    ------------------------------------------------------------------------
    -- Main Behaviour Process
    ------------------------------------------------------------------------
    Behaviour : PROCESS (RSTNeg, STRBNeg, RW, Address, DataIn, TDI, CLKIN,
                         TOENeg, TCKsig)

        -- Type definitions
        TYPE Reg_type IS ARRAY (7 downto 0) OF std_logic_vector(7 downto 0);
        TYPE fifo_type IS ARRAY (3 downto 0) OF std_logic_vector(7 downto 0);
        TYPE tap_state_type IS (Test_Logic_Reset,
                                Run_Test_Idle,
                                Select_DR_Scan,
                                Capture_DR,
                                Shift_DR,
                                Exit1_DR,
                                Pause_DR,
                                Exit2_DR,
                                Update_DR,
                                Select_IR_Scan,
                                Capture_IR,
                                Shift_IR,
                                Exit1_IR,
                                Pause_IR,
                                Exit2_IR,
                                Update_IR,
                                ASP,
                                ASP_in,
                                ASP_out
                               );

        -- Registers
        VARIABLE TAP_state  : tap_state_type;
        VARIABLE prev_state : tap_state_type;
        VARIABLE Reg   : Reg_type;
        ALIAS configA  : std_logic_vector(7 downto 0) IS Reg(0);
        ALIAS configB  : std_logic_vector(7 downto 0) IS Reg(1);
        ALIAS status   : std_logic_vector(7 downto 0) IS Reg(2);
        ALIAS command  : std_logic_vector(7 downto 0) IS Reg(3);
        ALIAS tdobuf   : std_logic_vector(7 downto 0) IS Reg(4);
        ALIAS tdibuf   : std_logic_vector(7 downto 0) IS Reg(5);
        ALIAS counter  : std_logic_vector(7 downto 0) IS Reg(6);
        ALIAS control  : std_logic_vector(7 downto 0) IS Reg(7);
        ALIAS NTOE     : UX01 IS configA(5);
        ALIAS LPBK     : std_logic_vector(1 downto 0) IS configA(4 downto 3);
        ALIAS MODE     : std_logic_vector(2 downto 0) IS configA(2 downto 0);
        ALIAS SWRST    : UX01 IS command(7);
        ALIAS NTRST    : UX01 IS command(6);
        ALIAS ENDST    : std_logic_vector(1 downto 0) IS command(5 downto 4);
        ALIAS TDIS     : UX01 IS status(7);
        ALIAS TDOS     : UX01 IS status(6);
        ALIAS CTRS     : UX01 IS status(5);
        ALIAS DNTR     : UX01 IS control(3);
        ALIAS DTMS     : UX01 IS control(2);
        ALIAS DTDI     : UX01 IS control(1);
        ALIAS DTDO     : UX01 IS control(0);
        VARIABLE CDIV    : natural;
        VARIABLE OPCOD   : natural;
        VARIABLE OP_done : boolean := true;
        VARIABLE TDI_on  : boolean := false;

        -- TDI FIFO
        VARIABLE TDI_fifo  : fifo_type;
        VARIABLE tdiincnt  : natural RANGE 0 to 3;
        VARIABLE tdioutcnt : natural RANGE 0 to 3;
        VARIABLE tdibitcnt : natural RANGE 0 to 7;

        -- TDO FIFO
        VARIABLE TDO_fifo  : fifo_type;
        VARIABLE TDO_empty : boolean := true;
        VARIABLE tdoincnt  : natural RANGE 0 to 3;
        VARIABLE tdooutcnt : natural RANGE 0 to 3;
        VARIABLE tdobitcnt : natural RANGE 0 to 7;

        -- TCK
        VARIABLE clkrun    : boolean := true;

        -- Counter
        VARIABLE Counter_reg : fifo_type;
        VARIABLE Count       : natural;
        VARIABLE countercnt  : natural RANGE 0 to 3;
        VARIABLE Count32     : std_logic_vector(31 downto 0);

        -- Timing Check Variables
        VARIABLE Tviol_A_STRBNeg_su  : X01 := '0';
        VARIABLE Tviol_A_STRBNeg_hd  : X01 := '0';
        VARIABLE TD_A_STRBNeg     : VitalTimingDataType;

        VARIABLE Tviol_D_STRBNeg  : X01 := '0';
        VARIABLE TD_D_STRBNeg     : VitalTimingDataType;

        VARIABLE Tviol_TDI_CLKIN  : X01 := '0';
        VARIABLE TD_TDI_CLKIN     : VitalTimingDataType;

        VARIABLE Tviol_RW_STRBNeg_su : X01 := '0';
        VARIABLE Tviol_RW_STRBNeg_hd : X01 := '0';
        VARIABLE TD_RW_STRBNeg    : VitalTimingDataType;

        VARIABLE Pviol_RSTNeg  : X01 := '0';
        VARIABLE PD_RSTNeg     : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_STRBNeg : X01 := '0';
        VARIABLE PD_STRBNeg    : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_CLKIN0  : X01 := '0';
        VARIABLE Pviol_CLKIN1  : X01 := '0';
        VARIABLE Pviol_CLKIN2  : X01 := '0';
        VARIABLE PD_CLKIN      : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Violation      : X01 := '0';

        -- Functionality Results Variables
        VARIABLE DOut_zd        : std_logic_vector(7 downto 0);
        VARIABLE RDYint         : std_ulogic;