tbstd8980.vhd

TDS510仿真器 的硬件电路和软件VHDL代码和大家共享.有兴趣可以自己动手做

--------------------------------------------------------------------------------
--  File Name: tbstd8980.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2001 Free Model Foundry; http:/vhdl.org/fmf/
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    01 Jan 08   initial release
--------------------------------------------------------------------------------
-- std8980 Test Bench
--------------------------------------------------------------------------------

LIBRARY IEEE;     USE IEEE.std_logic_1164.ALL;
                  USE IEEE.VITAL_timing.ALL;
                  USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;      USE FMF.gen_utils.ALL;
                  USE FMF.conversions.ALL;

ENTITY tbstd8980 IS END;

ARCHITECTURE test_1 of tbstd8980 IS

    COMPONENT std8980
        GENERIC (
        -- tipd delays: interconnect path delays
        tipd_D0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_RW                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_TDI                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLKIN               : VitalDelayType01 := VitalZeroDelay01;
        tipd_STRBNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_RSTNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_TOENeg              : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CLKIN_TDO            : VitalDelayType01 := UnitDelay01;
        tpd_CLKIN_TCK            : VitalDelayType01 := UnitDelay01;
        tpd_STRBNeg_D0           : VitalDelayType01Z := UnitDelay01Z;
        tpd_STRBNeg_RDY          : VitalDelayType01 := UnitDelay01;
        tpd_STRBNeg_TDO          : VitalDelayType01Z := UnitDelay01Z;
        tpd_STRBNeg_TMS          : VitalDelayType01Z := UnitDelay01Z;
        tpd_RSTNeg_D0            : VitalDelayType01 := UnitDelay01;
        tpd_RSTNeg_RDY           : VitalDelayType01 := UnitDelay01;
        tpd_RSTNeg_TDO           : VitalDelayType01 := UnitDelay01;
        tpd_RSTNeg_TCK           : VitalDelayType01 := UnitDelay01;
        tpd_TOENeg_TDO           : VitalDelayType01Z := UnitDelay01Z;
        -- tsetup values: setup times
        tsetup_D0_STRBNeg        : VitalDelayType := UnitDelay;
        tsetup_A0_STRBNeg        : VitalDelayType := UnitDelay;
        tsetup_RW_STRBNeg        : VitalDelayType := UnitDelay;
        tsetup_TDI_CLKIN         : VitalDelayType := UnitDelay;
        -- thold values: hold times
        thold_D0_STRBNeg         : VitalDelayType := UnitDelay;
        thold_A0_STRBNeg         : VitalDelayType := UnitDelay;
        thold_RW_STRBNeg         : VitalDelayType := UnitDelay;
        thold_TDI_CLKIN          : VitalDelayType := UnitDelay;
        -- tpw values: pulse widths
        tpw_CLKIN_z1          : VitalDelayType := UnitDelay;
        tpw_CLKIN_1z          : VitalDelayType := UnitDelay;
        tpw_CLKIN_z0          : VitalDelayType := UnitDelay;
        tpw_RSTNeg_negedge    : VitalDelayType := UnitDelay;
        tpw_STRBNeg_negedge   : VitalDelayType := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_CLKIN_z1      : VitalDelayType := UnitDelay;
        tperiod_CLKIN_1z      : VitalDelayType := UnitDelay;
        tperiod_CLKIN_z0      : VitalDelayType := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );

        PORT (
        D0              : INOUT std_ulogic := 'U';
        D1              : INOUT std_ulogic := 'U';
        D2              : INOUT std_ulogic := 'U';
        D3              : INOUT std_ulogic := 'U';
        D4              : INOUT std_ulogic := 'U';
        D5              : INOUT std_ulogic := 'U';
        D6              : INOUT std_ulogic := 'U';
        D7              : INOUT std_ulogic := 'U';
        A0              : IN    std_ulogic := 'U';
        A1              : IN    std_ulogic := 'U';
        A2              : IN    std_ulogic := 'U';
        RW              : IN    std_ulogic := 'U';
        TDI             : IN    std_ulogic := 'H';
        CLKIN           : IN    std_ulogic := 'U';
        RDY             : OUT   std_ulogic := 'U';
        TDO             : OUT   std_ulogic := 'U';
        TMS             : OUT   std_ulogic := 'U';
        TCK             : OUT   std_ulogic := 'U';
        STRBNeg         : IN    std_ulogic := 'H';
        RSTNeg          : IN    std_ulogic := 'H';
        TOENeg          : IN    std_ulogic := 'H';
        TRSTNeg         : OUT   std_ulogic := 'U'
    );
    END COMPONENT;

    for all : std8980 use entity WORK.std8980(VHDL_BEHAVIORAL);

--------------------------------------------------------------------------------
-- Tester Driven Signals
--------------------------------------------------------------------------------
    TYPE Test_type IS (Reg_rd, NTOE, CDIV, TDIS, TDI_buf, cnt_ld, CTRS, TDO_buf,
                  TDOS, tlr_rti, tlr_tlr, rti_pdr, rti_pir, reset, tlr_pdr,
                  tlr_pir, pir_shdr_pdr, pdr_shir_tlr, tlr_iirs_rti, rti_idrs_rti,
                  asp, asp_in, asp_out, dc, done);

    SIGNAL Test             : Test_type;
    SIGNAL T_D              : std_logic_vector(7 downto 0) := (others => 'Z');
    SIGNAL T_A              : std_logic_vector(2 downto 0);
    SIGNAL T_RW             : std_logic := 'U';
    SIGNAL T_TDI            : std_logic := 'U';
    SIGNAL T_CLKIN          : std_logic := '1';
    SIGNAL T_RDY            : std_logic := '1';
    SIGNAL T_TDO            : std_logic := 'U';
    SIGNAL T_TMS            : std_logic := 'U';
    SIGNAL T_TCK            : std_logic := 'U';
    SIGNAL T_STRBNeg        : std_logic := '1';
    SIGNAL T_RSTNeg         : std_logic := 'U';
    SIGNAL T_TOENeg         : std_logic := 'U';
    SIGNAL T_TRSTNeg        : std_logic := 'U';

BEGIN
    -- Functional Component
    std8980_1 : std8980
        GENERIC MAP(
            -- tipd delays: interconnect path delays
            tipd_D0 => VitalZeroDelay01,
            tipd_D1 => VitalZeroDelay01,
            tipd_D2 => VitalZeroDelay01,
            tipd_D3 => VitalZeroDelay01,
            tipd_D4 => VitalZeroDelay01,
            tipd_D5 => VitalZeroDelay01,
            tipd_D6 => VitalZeroDelay01,
            tipd_D7 => VitalZeroDelay01,
            tipd_A0 => VitalZeroDelay01,
            tipd_A1 => VitalZeroDelay01,
            tipd_A2 => VitalZeroDelay01,
            tipd_RW => VitalZeroDelay01,
            tipd_TDI => VitalZeroDelay01,
            tipd_CLKIN => VitalZeroDelay01,
            tipd_STRBNeg => VitalZeroDelay01,
            tipd_RSTNeg => VitalZeroDelay01,
            tipd_TOENeg => VitalZeroDelay01,
            -- tpd delays
            tpd_CLKIN_TDO => UnitDelay01,
            tpd_CLKIN_TCK => UnitDelay01,
            tpd_STRBNeg_D0 => UnitDelay01Z,
            tpd_STRBNeg_RDY => UnitDelay01,
            tpd_STRBNeg_TDO => UnitDelay01Z,
            tpd_STRBNeg_TMS => UnitDelay01Z,
            tpd_RSTNeg_D0 => UnitDelay01,
            tpd_RSTNeg_RDY => UnitDelay01,
            tpd_RSTNeg_TDO => UnitDelay01,
            tpd_RSTNeg_TCK => UnitDelay01,
            tpd_TOENeg_TDO => UnitDelay01Z,
            -- tsetup values: setup times
            tsetup_D0_STRBNeg => UnitDelay,
            tsetup_A0_STRBNeg => UnitDelay,
            tsetup_RW_STRBNeg => UnitDelay,
            tsetup_TDI_CLKIN => UnitDelay,
            -- thold values: hold times
            thold_D0_STRBNeg => UnitDelay,
            thold_A0_STRBNeg => UnitDelay,
            thold_RW_STRBNeg => UnitDelay,
            thold_TDI_CLKIN => UnitDelay,
            -- tpw values: pulse widths
            tpw_CLKIN_z1 => UnitDelay,
            tpw_CLKIN_1z => UnitDelay,
            tpw_CLKIN_z0 => UnitDelay,
            tpw_RSTNeg_negedge => UnitDelay,
            tpw_STRBNeg_negedge => UnitDelay,
            -- tperiod_min: minimum clock period = 1/max freq
            tperiod_CLKIN_z1 => UnitDelay,
            tperiod_CLKIN_1z => UnitDelay,
            tperiod_CLKIN_z0 => UnitDelay,
            -- generic control parameters
            InstancePath => DefaultInstancePath,
            TimingChecksOn => true,
            MsgOn => DefaultMsgOn,
            XOn => DefaultXon,
            -- For FMF SDF technology file usage
            TimingModel => "SN74LVT8980DW"
    )

        PORT MAP(
        D0             => T_D(0),
        D1             => T_D(1),
        D2             => T_D(2),
        D3             => T_D(3),
        D4             => T_D(4),
        D5             => T_D(5),
        D6             => T_D(6),
        D7             => T_D(7),
        A0             => T_A(0),
        A1             => T_A(1),
        A2             => T_A(2),
        RW             => T_RW,
        TDI            => T_TDI,
        CLKIN          => T_CLKIN,
        RDY            => T_RDY,
        TDO            => T_TDO,
        TMS            => T_TMS,
        TCK            => T_TCK,
        STRBNeg        => T_STRBNeg,
        RSTNeg         => T_RSTNeg,
        TOENeg         => T_TOENeg,
        TRSTNeg        => T_TRSTNeg
        );

T_TDI <= T_TDO AFTER 5 ns;

CLKGEN : PROCESS (T_CLKIN)
      BEGIN
        T_CLKIN <= not T_CLKIN AFTER 40 ns;
      END PROCESS CLKGEN;

Stim: PROCESS

    TYPE command_type IS (rd, wr);

    PROCEDURE Host
        (command : command_type;
         addr    : natural;
         word    : std_logic_vector(7 downto 0) := "00000000")

    IS
    
    BEGIN
        CASE command IS
            WHEN rd =>
                T_RW <= '1';
                T_A <= to_slv(addr, 3);
                WAIT FOR 12 ns;
                T_STRBNeg <= '0';
                WAIT FOR 17 ns;
                IF T_RDY = '0' THEN
                    WAIT UNTIL T_RDY = '1';
                END IF;
                T_STRBNeg <= '1';
            WHEN wr =>
                T_RW <= '0';
                T_A <= to_slv(addr, 3);
                WAIT FOR 12 ns;
                T_STRBNeg <= '0';
                T_D <= word;
                WAIT FOR 16 ns;
                IF T_RDY = '0' THEN
                    WAIT UNTIL T_RDY = '1';
                END IF;
                T_STRBNeg <= '1';
                WAIT FOR 16 ns;
                T_D <= "ZZZZZZZZ";
        END CASE;

    END Host;

    BEGIN
        T_TOENeg <= 'L';
        WAIT FOR 40 ns;
        T_RSTNeg <= 'L';
        WAIT FOR 40 ns;
        T_RSTNeg <= 'H';
        WAIT FOR 40 ns;
        Test <= Reg_rd;
        Host(rd,0);
        WAIT FOR 40 ns;
        Host(rd,1);
        WAIT FOR 40 ns;
        Host(rd,2);
        WAIT FOR 40 ns;

        Test <= NTOE;
        Host(wr,0,"00100000");
        WAIT FOR 40 ns;
        ASSERT (T_TDO = 'Z')
            REPORT "T_TDO is " & to_bin_str(T_TDO) & "should be Z"
            SEVERITY ERROR; 
        ASSERT (T_TMS = 'Z')
            REPORT "T_TMS is " & to_bin_str(T_TMS) & "should be Z"
            SEVERITY ERROR; 
        ASSERT (T_TCK = 'Z')
            REPORT "T_TCK is " & to_bin_str(T_TCK) & "should be Z"
            SEVERITY ERROR; 
        ASSERT (T_TRSTNeg = 'Z')
            REPORT "T_TRSTNeg is " & to_bin_str(T_TRSTNeg) & "should be Z"
            SEVERITY ERROR; 
        Host(wr,0,"00000000");
        WAIT FOR 400 ns;

        Test <= CDIV;
        Host(wr,1,"00000000");
        WAIT FOR 120 ns;
        Host(wr,1,"00100000");
        WAIT FOR 240 ns;

        Test <= TDIS;
        Host(rd,2);
        ASSERT (T_D = "00000000")
            REPORT "T_D is " & to_hex_str(T_D) & "should be 00000000"
            SEVERITY ERROR; 
        WAIT FOR 240 ns;