sdram.c

在AT91SAM7SE上测试sdram用的代码。

//Sdram.c

#include	"Preprocess.h"
#include	"SDRAM.h"



VOID AT91F_EBI_SDRAM_CfgPIO(VOID){
	
	// Configure PIO controllers to periph mode
	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA;
	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOA,	
		0,					
		AT91C_PA23_NWR1_NBS1_CFIOR_NUB 
			| AT91C_PA24_SDA10          
			| AT91C_PA25_SDCKE          
			| AT91C_PA26_NCS1_SDCS       
			| AT91C_PA27_SDWE           
			| AT91C_PA28_CAS            
			| AT91C_PA29_RAS 
	); 
	
	

	// Configure PIO controllers to periph mode
	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB;
	
	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOB, 
		0, 
		AT91C_PB1_A1_NBS2   
			| AT91C_PB16_A16_BA0  
			| AT91C_PB0_A0_NBS0   
			| AT91C_PB2_A2        
			| AT91C_PB3_A3        
			| AT91C_PB4_A4        
			| AT91C_PB10_A10      
			| AT91C_PB5_A5        
			| AT91C_PB11_A11      
			| AT91C_PB6_A6        
			| AT91C_PB12_A12      
			| AT91C_PB7_A7        
			| AT91C_PB13_A13      
			| AT91C_PB8_A8        
			| AT91C_PB14_A14      
			| AT91C_PB9_A9        
			| AT91C_PB15_A15      
			| AT91C_PB17_A17_BA1 
	); 

/*
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB0_A0_NBS0);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB1_A1_NBS2);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB2_A2);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB3_A3);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB4_A4);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB5_A5);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB6_A6);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB7_A7);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB8_A8);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB9_A9);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB10_A10);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB11_A11);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB12_A12);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB13_A13);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB14_A14);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB15_A15);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB16_A16_BA0);   
	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOB, 0, AT91C_PB17_A17_BA1);   
*/
	
	
	// Configure PIO controllers to periph mode
	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOC;
	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOC,
		AT91C_PC10_D10  
			| AT91C_PC11_D11  
			| AT91C_PC12_D12  
			| AT91C_PC13_D13  
			| AT91C_PC14_D14  
			| AT91C_PC15_D15  
			| AT91C_PC0_D0    
			| AT91C_PC1_D1    
			| AT91C_PC2_D2    
			| AT91C_PC3_D3    
			| AT91C_PC4_D4    
			| AT91C_PC5_D5    
			| AT91C_PC6_D6    
			| AT91C_PC7_D7    
			| AT91C_PC8_D8    
			| AT91C_PC9_D9,
		0
	);

}//VOID AT91F_EBI_SDRAM_CfgPIO(VOID)




VOID SdrInit (VOID){
    AT91PS_SDRC	psdrc = AT91C_BASE_SDRC;

    // Init the EBI for SDRAM
    AT91C_BASE_EBI -> EBI_CSA |=  AT91C_EBI_CS1A_SDRAMC;



	AT91F_EBI_SDRAM_CfgPIO();
	
    // Set Control Register
     psdrc->SDRC_CR =  AT91C_SDRC_NC_9           // 9  bits Column Addressing: 512 (A0-A8) AT91C_SDRC_NC_9
		| AT91C_SDRC_NR_13          			// 13 bits Row Addressing     8K (A0-12)  AT91C_SDRC_NR_13
		| AT91C_SDRC_CAS_2          			//  Check Table 8 for 7E(133) and 75(100) need CAS 2
		| AT91C_SDRC_NB_4_BANKS     			// 4 banks
		| AT91C_SDRC_TWR_2        
		| AT91C_SDRC_TRC_4        
		| AT91C_SDRC_TRP_4        
		| AT91C_SDRC_TRCD_3       
		| AT91C_SDRC_TRAS_3       
		| AT91C_SDRC_TXSR_4;
    // Wait time
   	Delay(10000);    

    // SDRAM Init step
	psdrc->SDRC_MR = AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_NOP_CMD;	// Set NOP
	*AT91C_SDRAM_BASE = 0x00000000;		                                // Perform NOP

	// // Set PRCHG ALL
	psdrc->SDRC_MR = AT91C_SDRC_DBW_16_BITS | 0x00000002;		        // Set PRCHG AL
	*AT91C_SDRAM_BASE	= 0x00000000;	                                // Perform PRCHG

	//8 Refresh Command.
	psdrc->SDRC_MR = AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 1st CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR = AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 2 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 3 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 4 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 5 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD;// Set 6 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD;// Set 7 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD;// Set 8 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	//Mode Register Command
	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_LMR_CMD;	// Set LMR operation
	*AT91C_SDRAM_BASE= 0x0;	                            				// Perform LMR burst=1, lat=2
	//*(AT91C_SDRAM_BASE  + 220)= 0xcafedede;	                        // Perform LMR burst=1, lat=2

	//Normal Mode Command
	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS ;    						// Set Normal mode // 16 bits
	*AT91C_SDRAM_BASE= 0x00000000;	              						// Perform Normal mode

    // Set Refresh Timer
	psdrc->SDRC_TR	= AT91C_SDRC_TR_TIME;


}//VOID SdrInit (VOID){