sdram.h

在AT91SAM7SE上测试sdram用的代码。

//Sdram.h


#ifndef		_SDRAM_H_
#define		_SDRAM_H_

#include	"type.h"
#include	"board.h"


// SDRAM Configuration.
#define		SDR_BYTE_PER_DEVICE			(32*1024*1024)
#define		SDR_BASE					(0x20000000)


#define		AT91C_SDRAM_BASE 			((volatile UINT *)SDR_BASE)
typedef		volatile BYTE				SDR_BYTE;

#define 	AT91C_SDRC_TWR_2    		((UINT) 0x2 <<  7) // (SDRC) Number of Write Recovery Time Cycles
#define 	AT91C_SDRC_TRC_4    		((UINT) 0x4 << 11) // (SDRC) Number of RAS Cycle Time Cycles 7
#define 	AT91C_SDRC_TRP_3    		((UINT) 0x3 << 15) // (SDRC) Number of RAS Precharge Time Cycles
#define 	AT91C_SDRC_TRP_4    		((UINT) 0x4 << 15) // (SDRC) Number of RAS Precharge Time Cycles
#define 	AT91C_SDRC_TRCD_3   		((UINT) 0x3 << 19) // (SDRC) Number of RAS to CAS Delay Cycles 2
#define 	AT91C_SDRC_TRAS_3   		((UINT) 0x3 << 23) // (SDRC) Number of RAS Active Time Cycles 5
#define 	AT91C_SDRC_TXSR_4   		((UINT) 0x4 << 27) // (SDRC) Number of Command Recovery Time Cycles 8

/*
#define 	AT91C_SDRC_TWR_2    		((UINT) 0x2 <<  7) // (SDRC) Number of Write Recovery Time Cycles
#define 	AT91C_SDRC_TRC_4    		((UINT) 0x4 << 11) // (SDRC) Number of RAS Cycle Time Cycles 7
#define 	AT91C_SDRC_TRP_4    		((UINT) 0x4 << 15) // (SDRC) Number of RAS Precharge Time Cycles
#define 	AT91C_SDRC_TRCD_2   		((UINT) 0x2 << 19) // (SDRC) Number of RAS to CAS Delay Cycles 2
#define 	AT91C_SDRC_TRAS_3   		((UINT) 0x3 << 23) // (SDRC) Number of RAS Active Time Cycles 5
#define 	AT91C_SDRC_TXSR_4   		((UINT) 0x4 << 27) // (SDRC) Number of Command Recovery Time Cycles 8
*/

/*
Refresh time 336 for 48MHz (TR= 15.6 * F ) 1/7 = 0.1428
Refresh period (8,192 rows)
Time 64ms	8192 row	Refresh period 7,8125	nb cycles 375,00

(64m/8192) / (1/48M) = 384
*/
#define		AT91C_SDRC_TR_TIME			375    // refresh time 384 ( 375+ 2%error)
#define		AT91C_SDRC_TR_TIME			(375 / 8)



VOID		AT91F_EBI_SDRAM_CfgPIO(VOID);
VOID		SdrInit (VOID);

#endif	 //_SDRAM_H_