clock.vhd

电子钟的源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity clock is

port(
	s0,s1:in std_logic;
	quickclk:in std_logic;
	slowclk:in std_logic;
	runclk:in std_logic;
	start:in std_logic;
	hh,lh,hm,lm,hs,ls:out std_logic_vector(3 downto 0 );
	seg:out std_logic_vector( 7 downto 0 );
	as,bs,cs,ds,es,fs,gs:out std_logic );
end clock;

architecture behave of clock is
	
	component downclk
	port(
		hclk:in std_logic;
		clk2to1:out std_logic );
	end component;

	component bcd7
	port(
		date:in std_logic_vector( 3 downto 0 );
		a,b,c,d,e,f,g:out std_logic );
	end component;

	component counter24
	port(
		clk,clr:in std_logic;
		low,high:out std_logic_vector(3 downto 0 ) );
	end component;

	component counter60
	port(
		clk,clr:in std_logic;
		low,high:out std_logic_vector( 3 downto 0 ) );
	end component;

	component mux8
	port(
		a,b,c,d,e,f:in std_logic_vector( 3 downto 0 );
		clk:in std_logic;
		sel:out std_logic_vector( 7 downto 0 );
		q:out std_logic_vector( 3 downto 0 ) );
	end component;

	signal sclk,mclk,hclk,clr,cclk:std_logic;
	signal hhour,lhour:std_logic_vector( 3 downto 0 );
	signal hmunite,lmunite:std_logic_vector( 3 downto 0 );
	signal hsecond,lsecond:std_logic_vector( 3 downto 0 );
	signal sel:std_logic_vector( 7 downto 0 );
	signal q: std_logic_vector( 3 downto 0 );

begin
	clr <= '0';

	u0:counter60 port map( sclk,clr,lsecond,hsecond );
	u1:counter60 port map( mclk,clr,lmunite,hmunite );
	u2:counter24 port map( hclk,clr,lhour,hhour );
	u3:mux8 port map( hhour,lhour,hmunite,lmunite,
						hsecond,lsecond,quickclk,sel,q );
	u4:bcd7 port map( q,as,bs,cs,ds,es,fs,gs );
	u5:downclk port map( slowclk,cclk );

	sclk <= ( runclk and s0 and s1 and (not start) ) 
		or ( start and cclk and (not s0) and s1 );
	mclk <= ( (not ((hsecond(2)) or hsecond(1) or hsecond(0) 
		or lsecond(3) or lsecond(2) or lsecond(1) 
		or lsecond(0))) and s0 and s1 and (not start) and ( not runclk ) ) 
		or ( start and cclk and s0 and (not s1) );
	hclk <= ( (not ((hmunite(2)) or hmunite(1) or hmunite(0) 
		or lmunite(3) or lmunite(2) or lmunite(1) 
		or lmunite(0))) and s0 and s1 and (not start) ) 
		or ( start and cclk and (not s1) and (not s0) );

	hh	<=	hhour;
	lh	<=	lhour;
	hm	<=	hmunite;
	lm	<=	lmunite;
	hs	<=	hsecond;
	ls	<=	lsecond;

	process( sel,s0,s1,slowclk )
	begin
		if ( s1 = '0' and s0 = '0' ) then
			seg(7) <= sel(7) and slowclk;
			seg(6) <= sel(6) and slowclk;
			seg( 5 downto 0 ) <= sel( 5 downto 0 );
		elsif ( s1 = '0' and s0 = '1' ) then
			seg( 7 downto 5 ) <= sel( 7 downto 5 );
			seg(4) <= sel(4) and slowclk;
			seg(3) <= sel(3) and slowclk;
			seg( 2 downto 0 ) <= sel( 2 downto 0 );
		elsif ( s1 = '1' and s0 = '0' ) then
			seg( 7 downto 2 ) <= sel( 7 downto 2 );
			seg(1) <= sel(1) and slowclk;
			seg(0) <= sel(0) and slowclk;
		elsif ( s1 = '1' and s0 = '1' ) then
			seg <= sel;
		else
			seg <= "00000000";
		end if;
	end process;
end behave;