bcd7.rpt

电子钟的源码

Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:d:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\bcd7.rpt
bcd7

** EQUATIONS **

date0    : INPUT;
date1    : INPUT;
date2    : INPUT;
date3    : INPUT;

-- Node name is 'a' 
-- Equation name is 'a', type is output 
a        =  _LC2_B8;

-- Node name is 'b' 
-- Equation name is 'b', type is output 
b        =  _LC6_B1;

-- Node name is 'c' 
-- Equation name is 'c', type is output 
c        =  _LC4_B8;

-- Node name is 'd' 
-- Equation name is 'd', type is output 
d        =  _LC1_B10;

-- Node name is 'e' 
-- Equation name is 'e', type is output 
e        =  _LC1_B8;

-- Node name is 'f' 
-- Equation name is 'f', type is output 
f        =  _LC3_B8;

-- Node name is 'g' 
-- Equation name is 'g', type is output 
g        =  _LC8_B1;

-- Node name is ':100' 
-- Equation name is '_LC5_B1', type is buried 
!_LC5_B1 = _LC5_B1~NOT;
_LC5_B1~NOT = LCELL( _EQ001);
  _EQ001 =  date0
         #  date3
         # !date2
         #  date1;

-- Node name is ':136' 
-- Equation name is '_LC6_B8', type is buried 
!_LC6_B8 = _LC6_B8~NOT;
_LC6_B8~NOT = LCELL( _EQ002);
  _EQ002 = !date0
         #  date3
         #  date1
         #  date2;

-- Node name is ':148' 
-- Equation name is '_LC5_B8', type is buried 
!_LC5_B8 = _LC5_B8~NOT;
_LC5_B8~NOT = LCELL( _EQ003);
  _EQ003 =  date0
         #  date2
         #  date1
         #  date3;

-- Node name is ':151' 
-- Equation name is '_LC2_B8', type is buried 
_LC2_B8  = LCELL( _EQ004);
  _EQ004 = !date1 & !date2 &  date3
         #  date1 & !date3
         #  date0 &  date2 & !date3
         # !date0 & !date1 & !date2;

-- Node name is '~187~1' 
-- Equation name is '~187~1', location is LC7_B1, type is buried.
-- synthesized logic cell 
_LC7_B1  = LCELL( _EQ005);
  _EQ005 =  date0 &  date1 &  date2 & !date3
         # !date1 & !date2;

-- Node name is ':187' 
-- Equation name is '_LC6_B1', type is buried 
_LC6_B1  = LCELL( _EQ006);
  _EQ006 =  _LC7_B1
         #  _LC5_B1
         #  _LC2_B1;

-- Node name is ':222' 
-- Equation name is '_LC8_B8', type is buried 
_LC8_B8  = LCELL( _EQ007);
  _EQ007 = !date1 & !date2 &  date3
         #  date0 &  date1 & !date3
         #  date2 & !date3;

-- Node name is ':223' 
-- Equation name is '_LC4_B8', type is buried 
_LC4_B8  = LCELL( _EQ008);
  _EQ008 =  _LC6_B8
         #  _LC5_B8
         #  _LC8_B8;

-- Node name is ':244' 
-- Equation name is '_LC4_B1', type is buried 
_LC4_B1  = LCELL( _EQ009);
  _EQ009 = !date0 &  date1 &  date2 & !date3
         #  date0 & !date1 &  date2 & !date3
         # !date1 & !date2 &  date3;

-- Node name is ':253' 
-- Equation name is '_LC1_B1', type is buried 
_LC1_B1  = LCELL( _EQ010);
  _EQ010 =  _LC4_B1 & !_LC5_B1
         #  _LC2_B1;

-- Node name is ':259' 
-- Equation name is '_LC1_B10', type is buried 
_LC1_B10 = LCELL( _EQ011);
  _EQ011 =  _LC1_B1 & !_LC6_B8
         #  _LC5_B8;

-- Node name is ':289' 
-- Equation name is '_LC7_B8', type is buried 
_LC7_B8  = LCELL( _EQ012);
  _EQ012 = !date0 & !date1 & !date2 &  date3
         # !date0 &  date1 & !date3;

-- Node name is ':295' 
-- Equation name is '_LC1_B8', type is buried 
_LC1_B8  = LCELL( _EQ013);
  _EQ013 = !_LC6_B8 &  _LC7_B8
         #  _LC5_B8;

-- Node name is ':331' 
-- Equation name is '_LC3_B8', type is buried 
_LC3_B8  = LCELL( _EQ014);
  _EQ014 = !date0 & !date1 & !date3
         # !date0 &  date2 & !date3
         # !date1 &  date2 & !date3
         # !date0 & !date1 & !date2
         # !date1 & !date2 &  date3;

-- Node name is '~361~1' 
-- Equation name is '~361~1', location is LC2_B1, type is buried.
-- synthesized logic cell 
_LC2_B1  = LCELL( _EQ015);
  _EQ015 =  date1 & !date2 & !date3;

-- Node name is '~369~1' 
-- Equation name is '~369~1', location is LC3_B1, type is buried.
-- synthesized logic cell 
_LC3_B1  = LCELL( _EQ016);
  _EQ016 = !date1 &  date2 & !date3
         # !date0 &  date2 & !date3
         # !date1 & !date2 &  date3
         # !date0 & !date2 &  date3;

-- Node name is ':369' 
-- Equation name is '_LC8_B1', type is buried 
_LC8_B1  = LCELL( _EQ017);
  _EQ017 =  _LC2_B1 & !_LC5_B8 & !_LC6_B8
         #  _LC3_B1 & !_LC5_B8 & !_LC6_B8;



Project Information  d:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\bcd7.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 17,585K