mux8.rpt

电子钟的源码

_LC6_C23~NOT = LCELL( _EQ006);
  _EQ006 =  state0
         #  state1
         # !state2;

-- Node name is ':473' 
-- Equation name is '_LC5_B18', type is buried 
_LC5_B18 = LCELL( _EQ007);
  _EQ007 =  _LC3_B18 & !_LC6_C23
         #  _LC1_C23 & !_LC6_C23
         #  c3 &  _LC6_C23;

-- Node name is ':480' 
-- Equation name is '_LC8_C20', type is buried 
!_LC8_C20 = _LC8_C20~NOT;
_LC8_C20~NOT = LCELL( _EQ008);
  _EQ008 = !state0
         # !state1
         #  state2;

-- Node name is ':490' 
-- Equation name is '_LC5_C20', type is buried 
!_LC5_C20 = _LC5_C20~NOT;
_LC5_C20~NOT = LCELL( _EQ009);
  _EQ009 =  state0
         # !state1
         #  state2;

-- Node name is ':493' 
-- Equation name is '_LC6_B18', type is buried 
_LC6_B18 = LCELL( _EQ010);
  _EQ010 =  _LC5_B18 & !_LC8_C20
         #  d3 &  _LC8_C20
         #  _LC5_C20;

-- Node name is ':500' 
-- Equation name is '_LC7_C20', type is buried 
!_LC7_C20 = _LC7_C20~NOT;
_LC7_C20~NOT = LCELL( _EQ011);
  _EQ011 = !state0
         #  state1
         #  state2;

-- Node name is ':503' 
-- Equation name is '_LC7_B18', type is buried 
_LC7_B18 = LCELL( _EQ012);
  _EQ012 =  _LC6_B18 & !_LC7_C20
         #  e3 &  _LC7_C20;

-- Node name is ':510' 
-- Equation name is '_LC3_C20', type is buried 
!_LC3_C20 = _LC3_C20~NOT;
_LC3_C20~NOT = LCELL( _EQ013);
  _EQ013 =  state0
         #  state1
         #  state2;

-- Node name is ':513' 
-- Equation name is '_LC1_B18', type is buried 
_LC1_B18 = LCELL( _EQ014);
  _EQ014 = !_LC3_C20 &  _LC7_B18
         #  f3 &  _LC3_C20;

-- Node name is ':519' 
-- Equation name is '_LC2_B18', type is buried 
_LC2_B18 = LCELL( _EQ015);
  _EQ015 =  a2 & !_LC6_C20
         #  b2 &  _LC6_C20;

-- Node name is ':525' 
-- Equation name is '_LC4_B18', type is buried 
_LC4_B18 = LCELL( _EQ016);
  _EQ016 = !_LC1_C23 &  _LC2_B18 & !_LC6_C23
         #  c2 &  _LC6_C23;

-- Node name is ':528' 
-- Equation name is '_LC6_A15', type is buried 
_LC6_A15 = LCELL( _EQ017);
  _EQ017 =  _LC4_B18 & !_LC8_C20
         #  d2 &  _LC8_C20;

-- Node name is ':534' 
-- Equation name is '_LC7_A15', type is buried 
_LC7_A15 = LCELL( _EQ018);
  _EQ018 = !_LC5_C20 &  _LC6_A15 & !_LC7_C20
         #  e2 &  _LC7_C20;

-- Node name is ':537' 
-- Equation name is '_LC1_A15', type is buried 
_LC1_A15 = LCELL( _EQ019);
  _EQ019 = !_LC3_C20 &  _LC7_A15
         #  f2 &  _LC3_C20;

-- Node name is '~546~1' 
-- Equation name is '~546~1', location is LC2_A15, type is buried.
-- synthesized logic cell 
_LC2_A15 = LCELL( _EQ020);
  _EQ020 =  a1 & !_LC6_C20
         #  b1 &  _LC6_C20;

-- Node name is ':549' 
-- Equation name is '_LC3_A15', type is buried 
_LC3_A15 = LCELL( _EQ021);
  _EQ021 =  _LC2_A15 & !_LC6_C23
         #  _LC1_C23 & !_LC6_C23
         #  c1 &  _LC6_C23;

-- Node name is ':555' 
-- Equation name is '_LC4_A15', type is buried 
_LC4_A15 = LCELL( _EQ022);
  _EQ022 =  _LC3_A15 & !_LC8_C20
         #  d1 &  _LC8_C20
         #  _LC5_C20;

-- Node name is ':558' 
-- Equation name is '_LC5_A15', type is buried 
_LC5_A15 = LCELL( _EQ023);
  _EQ023 =  _LC4_A15 & !_LC7_C20
         #  e1 &  _LC7_C20;

-- Node name is ':561' 
-- Equation name is '_LC8_A15', type is buried 
_LC8_A15 = LCELL( _EQ024);
  _EQ024 = !_LC3_C20 &  _LC5_A15
         #  f1 &  _LC3_C20;

-- Node name is ':567' 
-- Equation name is '_LC2_C23', type is buried 
_LC2_C23 = LCELL( _EQ025);
  _EQ025 =  a0 & !_LC6_C20
         #  b0 &  _LC6_C20;

-- Node name is ':573' 
-- Equation name is '_LC5_C23', type is buried 
_LC5_C23 = LCELL( _EQ026);
  _EQ026 = !_LC1_C23 &  _LC2_C23 & !_LC6_C23
         #  c0 &  _LC6_C23;

-- Node name is ':576' 
-- Equation name is '_LC7_C23', type is buried 
_LC7_C23 = LCELL( _EQ027);
  _EQ027 =  _LC5_C23 & !_LC8_C20
         #  d0 &  _LC8_C20;

-- Node name is ':582' 
-- Equation name is '_LC8_C23', type is buried 
_LC8_C23 = LCELL( _EQ028);
  _EQ028 = !_LC5_C20 & !_LC7_C20 &  _LC7_C23
         #  e0 &  _LC7_C20;

-- Node name is ':585' 
-- Equation name is '_LC3_C23', type is buried 
_LC3_C23 = LCELL( _EQ029);
  _EQ029 = !_LC3_C20 &  _LC8_C23
         #  f0 &  _LC3_C20;

-- Node name is ':611' 
-- Equation name is '_LC4_C20', type is buried 
_LC4_C20 = LCELL( _EQ030);
  _EQ030 =  state0 &  state1 &  state2;



Project Information  d:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\mux8.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 20,733K