downclk.vhd

来自「电子钟的源码」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;

entity downclk is

port(
	hclk:in std_logic;
	clk2to1:out std_logic );
end downclk;

architecture behave of downclk is

signal a:integer range 0 to 1;

begin

	process( a,hclk )
	begin
		if ( hclk'event and hclk = '1' ) then
			if ( a = 1) then
				a <= 0;
				clk2to1 <= '1';
			elsif ( a >= 0 and a <= 1 ) then
				a <= a + 1;
				clk2to1 <= '0';
			end if;
		end if;
	end process;

end;