x240x.h

一个DSP2407读取PUDID12USB芯片的源码

CANMBX2C	.set 7216h	; CAN 2 of 8 bytes of Mailbox 2	
CANMBX2D	.set 7217h	; CAN 2 of 8 bytes of Mailbox 2	
CANMSGID3L	.set 7218h	; CAN Message ID for mailbox 3 (lower 16 bits)	
CANMSGID3H	.set 7219h	; CAN Message ID for mailbox 3 (upper 16 bits)	
CANMSGCTRL3	.set 721Ah	; CAN RTR and DLC	
CANMBX3A	.set 721Ch	; CAN 2 of 8 bytes of Mailbox 3	
CANMBX3B	.set 721Dh	; CAN 2 of 8 bytes of Mailbox 3	
CANMBX3C	.set 721Eh	; CAN 2 of 8 bytes of Mailbox 3	
CANMBX3D	.set 721Fh	; CAN 2 of 8 bytes of Mailbox 3	
CANMSGID4L	.set 7220h	; CAN Message ID for mailbox 4 (lower 16 bits)	
CANMSGID4H	.set 7221h	; CAN Message ID for mailbox 4 (upper 16 bits)	
CANMSGCTRL4	.set 7222h	; CAN RTR and DLC	
CANMBX4A	.set 7224h	; CAN 2 of 8 bytes of Mailbox 4	
CANMBX4B	.set 7225h	; CAN 2 of 8 bytes of Mailbox 4	
CANMBX4C	.set 7226h	; CAN 2 of 8 bytes of Mailbox 4	
CANMBX4D	.set 7227h	; CAN 2 of 8 bytes of Mailbox 4	
CANMSGID5L	.set 7228h	; CAN Message ID for mailbox 5 (lower 16 bits)	
CANMSGID5H	.set 7229h	; CAN Message ID for mailbox 5 (upper 16 bits)	
CANMSGCTRL5	.set 722Ah	; CAN RTR and DLC	
CANMBX5A	.set 722Ch	; CAN 2 of 8 bytes of Mailbox 5	
CANMBX5B	.set 722Dh	; CAN 2 of 8 bytes of Mailbox 5	
CANMBX5C	.set 722Eh	; CAN 2 of 8 bytes of Mailbox 5	

; Event Manager A  (EVA) registers 
GPTCONA		.set 7400h	; GP Timer control register A . 
GPTCON  	.set 7400h  ; General Timer Control
T1CNT		.set 7401h	; GP Timer 1 counter register. 
T1CMPR		.set 7402h	; GP Timer 1 compare register. 
T1CMP       .set 7402h  ; T1 Compare Value
T1PR		.set 7403h	; GP Timer 1 period register. 
T1PER       .set 7403h  ; T1 Period
T1CON		.set 7404h	; GP Timer 1 control register. 
T2CNT		.set 7405h	; GP Timer 2 counter register. 
T2CMPR		.set 7406h	; GP Timer 2 compare register. 
T2CMP       .set 7406h  ; T2 Compare Value
T2PR		.set 7407h	; GP Timer 2 period register. 
T2PER       .set 7407h  ; T2 Period
T2CON		.set 7408h	; GP Timer 2 control register. 

COMCONA		.set 7411h	; Compare control register A.
COMCON      .set 7411h  ; Compare Control
ACTRA		.set 7413h	; Full compare action control register A.
ACTR        .set 7413h  ; Compare Output Action Control (240 Only)
SACTR       .set 7414h  ; S Comp Output Action Control (240 Only)
DBTCONA		.set 7415h	; Dead-band timer control register A. 
DBTCON      .set 7415h  ; Dead Band Control

CMPR1		.set 7417h	; Full compare unit compare register1 A. 
CMPR2		.set 7418h	; Full compare unit compare register2 A.
CMPR3		.set 7419h	; Full compare unit compare register3 A.

SCMPR1  	.set 741Ah  ; S Comp Value 1 (240 Only)
SCMPR2  	.set 741Bh  ; S Comp Value 2 (240 Only)
SCMPR3  	.set 741Ch  ; S Comp Value 3 (240 Only)


CAPCONA		.set 7420h	; Capture control register A. 
CAPCON  	.set 7420h  ; Capture Control
CAPFIFOA 	.set 7422h	; Capture FIFO status register A. 
CAPFIFO     .set 7422h  ; Capture FIFO1-3/4 Status
			
CAP1FIFO	.set 7423h	; Capture Channel 1 FIFO Top 
FIFO1       .set 7423h  ; Capture 1 FIFO Top
CAP2FIFO	.set 7424h	; Capture Channel 2 FIFO Top 
FIFO2       .set 7424h  ; Capture 2 FIFO Top
CAP3FIFO	.set 7425h	; Capture Channel 3 FIFO Top 
FIFO3       .set 7425h  ; Capture 3 FIFO Top
FIFO4       .set 7426h  ; Capture 4 FIFO Top (240 Only)

CAP1FBOT	.set 7427h	; Bottom reg. pf capture FIFO stack 1 A
FIFOBT1 	.set 7427h  ; Capture 1 FIFO Bottom (240x only)
CAP2FBOT	.set 7428h	; Bottom reg. pf capture FIFO stack 2 A
FIFOBT2 	.set 7428h  ; Capture 2 FIFO Bottom (240x only)
CAP3FBOT	.set 7429h	; Bottom reg. pf capture FIFO stack 3 A
FIFOBT3     .set 7429h  ; Capture 3 FIFO Bottom (240x only)

EVAIMRA		.set 742Ch	; Group A Interrupt Mask Register A
EVIMRA  	.set 742Ch  ; Group A Int Mask
IMRA        .set 742Ch  ; Group A Int Mask
EVAIMRB		.set 742Dh	; Group B Interrupt Mask Register A
EVIMRB  	.set 742Dh  ; Group B Int Mask
IMRB        .set 742Dh  ; Group B Int Mask
EVAIMRC		.set 742Eh	; Group C Interrupt Mask Register A
EVIMRC  	.set 742Eh  ; Group C Int Mask
IMRC        .set 742Eh  ; Group C Int Mask

EVAIFRA		.set 742Fh	; Group A Interrupt Flag Register A
EVIFRA  	.set 742Fh  ; Group A Int Flag
IFRA        .set 742Fh  ; Group A Int Flag
EVAIFRB		.set 7430h	; Group B Interrupt Flag Register A
EVIFRB  	.set 7430h  ; Group B Int Flag
IFRB        .set 7430h  ; Group B Int Flag
EVAIFRC		.set 7431h	; Group C Interrupt Flag Register A
EVIFRC  	.set 7431h  ; Group C Int Flag
IFRC        .set 7431h  ; Group C Int Flag

EVIVRA  	.set 7432h  ; Group A Int ID (x240 only)
IVRA        .set 7432h  ; Group A Int ID (x240 only)
EVIVRB  	.set 7433h  ; Group B Int ID (x240 only)
IVRB        .set 7433h  ; Group B Int ID (x240 only)
EVIVRC  	.set 7434h  ; Group C Int ID (x240 only)
IVRC        .set 7434h  ; Group C Int ID (x240 only)

; Event Manager B (EVB) Registers (240x Only) 
GPTCONB		.set 7500h	; GP Timer control register B . 
T3CNT		.set 7501h	; GP Timer 3 counter register. 
T3CNTB  	.set 7501h  ; T1 Counter
T3CMPR		.set 7502h	; GP Timer 3 compare register. 
T3CMPB  	.set 7502h  ; T1 Comp Value
T3PR		.set 7503h	; GP Timer 3 period register. 
T3PERB  	.set 7503h  ; T1 Period
T3CON		.set 7504h	; GP Timer 3 control register. 
T3CONB  	.set 7504h  ; T1 Control
T4CNT		.set 7505h	; GP Timer 4 counter register. 
T4CNTB  	.set 7505h  ; T2 Counter
T4CMPR		.set 7506h	; GP Timer 4 compare register. 
T4CMPB  	.set 7506h  ; T2 Comp Value
T4PR		.set 7507h	; GP Timer 4 period register. 
T4PERB  	.set 7507h  ; T2 Period
T4CON		.set 7508h	; GP Timer 4 control register. 
T4CONB  	.set 7508h  ; T2 Control

COMCONB		.set 7511h	; Compare control register B.
ACTRB		.set 7513h	; Full compare action control register B.
DBTCONB		.set 7515h	; Dead-band timer control register B. 

CMPR4		.set 7517h	; Full compare unit compare register1 B. 
CMPR4B  	.set 7517h  ; Comp Value 4
CMPR5		.set 7518h	; Full compare unit compare register2 B.
CMPR5B  	.set 7518h  ; Comp Value 5
CMPR6		.set 7519h	; Full compare unit compare register3 B.
CMPR6B  	.set 7519h  ; Comp Value 6

CAPCONB		.set 7520h	; Capture control register B. 
CAPFIFOB 	.set 7522h	; Capture FIFO status register B. 
			
CAP4FIFO	.set 7523h	; Capture Channel 1 FIFO Top B
FIFO4B  	.set 7523h  ; Capture 4 FIFO Top
CAP5FIFO	.set 7524h	; Capture Channel 2 FIFO Top B
FIFO5B  	.set 7524h  ; Capture 5 FIFO Top
CAP6FIFO	.set 7525h	; Capture Channel 3 FIFO Top B
FIFO6B  	.set 7525h  ; Capture 6 FIFO Top

CAP4FBOT	.set 7527h	; Bottom reg. pf capture FIFO stack 1 B
FIFOBT4B    .set 7527h  ; Capture 4 FIFO Bottom
CAP5FBOT	.set 7528h	; Bottom reg. pf capture FIFO stack 2 B
FIFOBT5B    .set 7528h  ; Capture 5 FIFO Bottom
CAP6FBOT	.set 7529h	; Bottom reg. pf capture FIFO stack 3 B
FIFOBT6B    .set 7529h  ; Capture 6 FIFO Bottom

EVBIMRA		.set 752Ch	; Group A Interrupt Mask Register B
IMRAB       .set 752Ch  ; Group A Int Mask
EVBIMRB		.set 752Dh	; Group B Interrupt Mask Register B
IMRBB       .set 752Dh  ; Group B Int Mask
EVBIMRC		.set 752Eh	; Group C Interrupt Mask Register B
IMRCB       .set 752Eh  ; Group C Int Mask

EVBIFRA		.set 752Fh	; Group A Interrupt Flag Register B
IFRAB       .set 752Fh  ; Group A Int Flag
EVBIFRB		.set 7530h	; Group B Interrupt Flag Register B
IFRBB       .set 7530h  ; Group B Int Flag
EVBIFRC		.set 7531h	; Group C Interrupt Flag Register B
IFRCB       .set 7531h  ; Group C Int Flag

;-------------------------------------------------------------
; I/O space mapped registers
;-------------------------------------------------------------
WSGR		.set 0FFFFh	; Wait-State Generator Control Reg
FCMR		.set 0FF0Fh	; Flash control mode register

;-----------------------------------------------------------------------------
; Constant defines
;-----------------------------------------------------------------------------
B0_SADDR    .set  0200h ; Block B0 start address
B0_EADDR    .set  02FFh ; Block B0 end address
B1_SADDR    .set  0300h ; Block B1 start address
B1_EADDR    .set  03FFh ; Block B1 end address
B2_SADDR    .set  0060h ; Block B2 start address
B2_EADDR    .set  007Fh ; Block B2 end address

;External Data Space Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
EXTDATA 	.set  8000h

;--------------------------------------------------------------
; Bit codes for Test bit instruction (BIT) (15 Loads bit 0 into TC)
;-------------------------------------------------------------
BIT15		.set 0000h	; Bit Code for 15
BIT14		.set 0001h	; Bit Code for 14
BIT13		.set 0002h	; Bit Code for 13
BIT12		.set 0003h	; Bit Code for 12
BIT11		.set 0004h	; Bit Code for 11
BIT10		.set 0005h	; Bit Code for 10
BIT9		.set 0006h	; Bit Code for 9
BIT8		.set 0007h	; Bit Code for 8
BIT7		.set 0008h	; Bit Code for 7
BIT6		.set 0009h	; Bit Code for 6
BIT5		.set 000Ah	; Bit Code for 5
BIT4		.set 000Bh	; Bit Code for 4
BIT3		.set 000Ch	; Bit Code for 3
BIT2		.set 000Dh	; Bit Code for 2
BIT1		.set 000Eh	; Bit Code for 1
BIT0		.set 000Fh	; Bit Code for 0

;--------------------------------------------------------------------------
;Test mode on and off constants
;--------------------------------------------------------------------------
ABRPT   	.set 001fh  ; Analysis BreakPoint Register
PSA_ON	   	.set 03A1h	; Turn PSA and FEEDB on
PSA_FB_OFF 	.set 0121h  ; Turn PSA and FEEDB off

wd_rst_1    .set 0055h  ; watchdog timer reset string
wd_rst_2    .set 00AAh  ; watchdog timer reset string