📄 x240x.h
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; ==================================================================================
; File name: x240x.h
;
; Originator: Digital Control Systems Group
; Texas Instruments
;
; Description:
; X240x Peripheral Registers + other useful definitions
; =====================================================================================
; History:
; -------------------------------------------------------------------------------------
; 9-15-2000 Release Rev 1.0
; ------------------------------------------------------------------------------------
; 24xx core registers
IMR .set 0004h ; Interrupt Mask Register
GREG .set 0005h ; Global memory allocation Register
IFR .set 0006h ; Interrupt Flag Register
; System configuration and interrupt registers
PIRQR0 .set 7010h ; Periph Interrupt Request Reg 0.
PIRQR1 .set 7011h ; Periph Interrupt Request Reg 1.
PIRQR2 .set 7012h ; Periph Interrupt Request Reg 2.
PIACKR0 .set 7014h ; Periph Interrupt Acknowledge Reg 0.
PIACKR1 .set 7015h ; Periph Interrupt Acknowledge Reg 1.
PIACKR2 .set 7016h ; Periph Interrupt Acknowledge Reg 2.
SCSR1 .set 7018h ; System Control & Status Reg. 1 (x240x only)
SSCR .set 7018h ; System Status & Control reg (x241/2/3 only)
SCSR .set 7018h ; System Status & Control reg (x241/2/3 only)
SYSCR .set 7018h ; System Control (x240 only)
SCSR2 .set 7019h ; System Control & Status Reg. 2 (x240x only)
SYSSR .set 701Ah ; System Status (x240 only)
DINR .set 701Ch ; Device Identification Register.
DIN .set 701Ch ; Device Identification Register
PIVR .set 701Eh ; Peripheral Interrupt Vector Reg.
SYSIVR .set 701Eh ; System Int Vector (x240 only)
;Watch-Dog(WD) / Real Time Int(RTI) / Phase Lock Loop(PLL) Registers
RTI_CNTR .set 7021h ; RTI Counter reg
RTICNTR .set 7021h ; RTI Counter reg (x240 only)
WD_CNTR .set 7023h ; WD Counter reg
WDCNTR .set 7023h ; WD Counter reg
WD_KEY .set 7025h ; WD Key reg
WDKEY .set 7025h ; WD Key reg
RTI_CNTL .set 7027h ; RTI Control reg
RTICR .set 7027h ; RTI Control reg (x240 only)
WD_CNTL .set 7029h ; WD Control reg
WDCR .set 7029h ; WD Control reg
CKCR0 .set 702Ah ; PLL Clock Control 0 (X240 only)
PLL_CNTL1 .set 702Bh ; PLL control reg 1
CKCR1 .set 702Ch ; PLL Clock Control 1 (X240 only)
PLL_CNTL2 .set 702Dh ; PLL control reg 2
; SPI registers
SPICCR .set 7040h ; SPI Config Control Reg
SPI_CCR .set 7040h ; SPI Config Control Reg 1
SPICTL .set 7041h ; SPI Operation Control Reg
SPI_CTL .set 7041h ; SPI Operation Control Reg 2
SPISTS .set 7042h ; SPI Status Reg
SPI_STS .set 7042h ; SPI Status Reg
SPIBRR .set 7044h ; SPI Baud rate control reg
SPI_BRR .set 7044h ; SPI Baud rate control reg
SPIRXEMU .set 7046h ; SPI Emulation buffer reg
SPI_EMU .set 7046h ; SPI Emulation buffer reg
SPIRXBUF .set 7047h ; SPI Serial receive buffer reg
SPI_BUF .set 7047h ; SPI Serial Input buffer reg
SPITXBUF .set 7048h ; SPI Serial transmit buffer reg
SPIDAT .set 7049h ; SPI Serial data reg
SPI_DAT .set 7049h ; SPI Serial Data reg
SPIPC1 .set 704Dh ; SPI Port control reg1
SPI_PC1 .set 704Dh ; SPI Port control reg1
SPIPC2 .set 704Eh ; SPI Port control reg2
SPI_PC2 .set 704Eh ; SPI Port control reg2
SPIPRI .set 704Fh ; SPI Priority control reg
SPI_PRI .set 704Fh ; SPI Priority control reg
; SCI registers
SCICCR .set 7050h ; SCI Communication control reg
SCI_CCNTL .set 7050h ; SCI Comms Control Reg
SCICTL1 .set 7051h ; SCI Control reg1
SCI_CNTL1 .set 7051h ; SCI Control Reg 1
SCIHBAUD .set 7052h ; SCI Baud Rate MSbyte reg
SCI_HBAUD .set 7052h ; SCI Baud rate control
SCILBAUD .set 7053h ; SCI Baud Rate LSbyte reg
SCI_LBAUD .set 7053h ; SCI Baud rate control
SCICTL2 .set 7054h ; SCI Control reg2
SCI_CNTL2 .set 7054h ; SCI Control Reg 2
SCIRXST .set 7055h ; SCI Receiver Status reg
SCI_RX_STAT .set 7055h ; SCI Receive status reg
SCIRXEMU .set 7056h ; SCI Emulation Data Buffer reg
SCI_RX_EMU .set 7056h ; SCI EMU data buffer
SCIRXBUF .set 7057h ; SCI Receiver Data buffer reg
SCI_RX_BUF .set 7057h ; SCI Receive data buffer
SCITXBUF .set 7059h ; SCI Transmit Data buffer reg
SCI_TX_BUF .set 7059h ; SCI Transmit data buffer
SCI_PORT_C1 .set 705Dh ; SCI Port control reg1
SCI_PORT_C2 .set 705Eh ; SCI Port control reg2
SCIPC2 .set 705Eh ; SCI Port control reg2 (x240 only)
SCI_PRI .set 705Fh ; SCI Priority control reg
SCIPRI .set 705Fh ; SCI Priority control reg
; External interrupt configuration registers
XINT1CR240 .set 7070h ; Int1 (type A) config (X240 only)
XINT1CR .set 7070h ; Ext. interrupt 1 config reg for X241/2/3 only.
XINT1_CNTL .set 7070h ; Int1 (type A) Control reg
XINT2CR .set 7071h ; External interrupt 2 config. X241/2/3 only.
XINT2CR241 .set 7071h ; External interrupt 2 config. X241/2/3 only.
NMICR .set 7072h ; NMI (type A) config (X240 only)
NMI_CNTL .set 7072h ; Non maskable Int (type A) Control reg
XINT2CR240 .set 7078h ; Int2 (type C) config (X240 only)
XINT2_CNTL .set 7078h ; Int2 (type C) Control reg
XINT3CR240 .set 707Ah ; Int3 (type C) config (X240 only)
XINT3_CNTL .set 707Ah ; Int3 (type C) Control reg
XINT3CR .set 707Ah ; Ext. interrupt 1 config reg for X240 only.
; Digital I/O registers
MCRA .set 7090h ; Output Control Reg A
OCRA .set 7090h ; Output Control A
MCRB .set 7092h ; Output Control Reg B
OCRB .set 7092h ; Output Control B
MCRC .set 7094h ; Output Control Reg C
OCRC .set 7094h ; Output control C (X240x only)
ISRA .set 7094h ; Input Status A (X240 only)
IPSRA .set 7094h ; Input Status Reg A
ISRB .set 7096h ; Input Status B (X240 only)
IPSRB .set 7096h ; Input Status Reg B
PADATDIR .set 7098h ; I/O port A Data & Direction reg.
PBDATDIR .set 709Ah ; I/O port B Data & Direction reg.
PCDATDIR .set 709Ch ; I/O port C Data & Direction reg.
PDDATDIR .set 709Eh ; I/O port D Data & Direction reg.
PEDATDIR .set 7095h ; I/O port E Data & Direction reg.
PFDATDIR .set 7096h ; I/O port F Data & Direction reg.
; Analog-to-Digital Converter(ADC) registers - x240x
ADCTRL1 .set 70A0h ; ADC Control Reg1
ADCL_CNTL1 .set 70A0h ; ADC Control reg 1
ADCTRL2 .set 70A1h ; ADC Control Reg2
ADCL_CNTL2 .set 70A1h ; ADC Control reg 2
MAXCONV .set 70A2h ; Maximum conversion channels register
CHSELSEQ1 .set 70A3h ; Channel select Sequencing control register 1
CHSELSEQ2 .set 70A4h ; Channel select Sequencing control register 2
CHSELSEQ3 .set 70A5h ; Channel select Sequencing control register 3
CHSELSEQ4 .set 70A6h ; Channel select Sequencing control register 4
AUTO_SEQ_SR .set 70A7h ; Auto-sequence status register
RESULT0 .set 70A8h ; Conversion result buffer register 0
ADC_RESULT0 .set 70A8h ; Conversion result buffer register 0
RESULT1 .set 70A9h ; Conversion result buffer register 1
ADC_RESULT1 .set 70A9h ; Conversion result buffer register 1
RESULT2 .set 70AAh ; Conversion result buffer register 2
ADC_RESULT2 .set 70AAh ; Conversion result buffer register 2
RESULT3 .set 70ABh ; Conversion result buffer register 3
ADC_RESULT3 .set 70ABh ; Conversion result buffer register 3
RESULT4 .set 70ACh ; Conversion result buffer register 4
ADC_RESULT4 .set 70ACh ; Conversion result buffer register 4
RESULT5 .set 70ADh ; Conversion result buffer register 5
ADC_RESULT5 .set 70ADh ; Conversion result buffer register 5
RESULT6 .set 70AEh ; Conversion result buffer register 6
ADC_RESULT6 .set 70AEh ; Conversion result buffer register 6
RESULT7 .set 70AFh ; Conversion result buffer register 7
ADC_RESULT7 .set 70AFh ; Conversion result buffer register 7
RESULT8 .set 70B0h ; Conversion result buffer register 8
ADC_RESULT8 .set 70B0h ; Conversion result buffer register 8
RESULT9 .set 70B1h ; Conversion result buffer register 9
RESULT10 .set 70B2h ; Conversion result buffer register 10
ADC_RESULT10 .set 70B2h ; Conversion result buffer register 10
RESULT11 .set 70B3h ; Conversion result buffer register 11
ADC_RESULT11 .set 70B3h ; Conversion result buffer register 11
RESULT12 .set 70B4h ; Conversion result buffer register 12
ADC_RESULT12 .set 70B4h ; Conversion result buffer register 12
RESULT13 .set 70B5h ; Conversion result buffer register 13
ADC_RESULT13 .set 70B5h ; Conversion result buffer register 13
RESULT14 .set 70B6h ; Conversion result buffer register 14
ADC_RESULT14 .set 70B6h ; Conversion result buffer register 14
RESULT15 .set 70B7h ; Conversion result buffer register 15
ADC_RESULT15 .set 70B7h ; Conversion result buffer register 15
CALIBRATION .set 70B8h ; Calib result, used to correct subsequent conversions
; CAN(SCC) registers.
CANMDER .set 7100h ; CAN Mailbox Direction/Enable reg
CANTCR .set 7101h ; CAN Transmission Control Reg
CANRCR .set 7102h ; CAN Recieve COntrol Reg
CANMCR .set 7103h ; CAN Master Control Reg
CANBCR2 .set 7104h ; CAN Bit COnfig Reg 2
CANBCR1 .set 7105h ; CAN Bit Config Reg 1
CANESR .set 7106h ; CAN Error Status Reg
CANGSR .set 7107h ; CAN Global Status Reg
CANCEC .set 7108h ; CAN Trans and Rcv Err counters
CANIFR .set 7109h ; CAN Interrupt Flag Registers
CANIMR .set 710Ah ; CAN Interrupt Mask Registers
CANLAM0H .set 710Bh ; CAN Local Acceptance Mask MBx0/1
CANLAM0L .set 710Ch ; CAN Local Acceptance Mask MBx0/1
CANLAM1H .set 710Dh ; CAN Local Acceptance Mask MBx2/3
CANLAM1L .set 710Eh ; CAN Local Acceptance Mask MBx2/3
CANMSGID0L .set 7200h ; CAN Message ID for mailbox 0 (lower 16 bits)
CANMSGID0H .set 7201h ; CAN Message ID for mailbox 0 (upper 16 bits)
CANMSGCTRL0 .set 7202h ; CAN RTR and DLC
CANMBX0A .set 7204h ; CAN 2 of 8 bytes of Mailbox 0
CANMBX0B .set 7205h ; CAN 2 of 8 bytes of Mailbox 0
CANMBX0C .set 7206h ; CAN 2 of 8 bytes of Mailbox 0
CANMBX0D .set 7207h ; CAN 2 of 8 bytes of Mailbox 0
CANMSGID1L .set 7208h ; CAN Message ID for mailbox 1 (lower 16 bits)
CANMSGID1H .set 7209h ; CAN Message ID for mailbox 1 (upper 16 bits)
CANMSGCTRL1 .set 720Ah ; CAN RTR and DLC
CANMBX1A .set 720Ch ; CAN 2 of 8 bytes of Mailbox 1
CANMBX1B .set 720Dh ; CAN 2 of 8 bytes of Mailbox 1
CANMBX1C .set 720Eh ; CAN 2 of 8 bytes of Mailbox 1
CANMBX1D .set 720Fh ; CAN 2 of 8 bytes of Mailbox 1
CANMSGID2L .set 7210h ; CAN Message ID for mailbox 2 (lower 16 bits)
CANMSGID2H .set 7211h ; CAN Message ID for mailbox 2 (upper 16 bits)
CANMSGCTRL2 .set 7212h ; CAN RTR and DLC
CANMBX2A .set 7214h ; CAN 2 of 8 bytes of Mailbox 2
CANMBX2B .set 7215h ; CAN 2 of 8 bytes of Mailbox 2
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